1 /* 2 * DMA support for Internal DMAC with SDHI SD/SDIO controller 3 * 4 * Copyright (C) 2016-17 Renesas Electronics Corporation 5 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/device.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/io-64-nonatomic-hi-lo.h> 16 #include <linux/mfd/tmio.h> 17 #include <linux/mmc/host.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/pagemap.h> 21 #include <linux/scatterlist.h> 22 #include <linux/sys_soc.h> 23 24 #include "renesas_sdhi.h" 25 #include "tmio_mmc.h" 26 27 #define DM_CM_DTRAN_MODE 0x820 28 #define DM_CM_DTRAN_CTRL 0x828 29 #define DM_CM_RST 0x830 30 #define DM_CM_INFO1 0x840 31 #define DM_CM_INFO1_MASK 0x848 32 #define DM_CM_INFO2 0x850 33 #define DM_CM_INFO2_MASK 0x858 34 #define DM_DTRAN_ADDR 0x880 35 36 /* DM_CM_DTRAN_MODE */ 37 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 38 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "uptream" = for read commands */ 39 #define DTRAN_MODE_BUS_WID_TH (BIT(5) | BIT(4)) 40 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */ 41 42 /* DM_CM_DTRAN_CTRL */ 43 #define DTRAN_CTRL_DM_START BIT(0) 44 45 /* DM_CM_RST */ 46 #define RST_DTRANRST1 BIT(9) 47 #define RST_DTRANRST0 BIT(8) 48 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 49 50 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 51 #define INFO1_CLEAR 0 52 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 53 #define INFO1_DTRANEND1 BIT(17) 54 #define INFO1_DTRANEND0 BIT(16) 55 56 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 57 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 58 #define INFO2_DTRANERR1 BIT(17) 59 #define INFO2_DTRANERR0 BIT(16) 60 61 /* 62 * Specification of this driver: 63 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 64 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 65 * need a custom accessor. 66 */ 67 68 static unsigned long global_flags; 69 /* 70 * Workaround for avoiding to use RX DMAC by multiple channels. 71 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 72 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 73 * stored into the system memory even if the DMAC interrupt happened. 74 * So, this driver then uses one RX DMAC channel only. 75 */ 76 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 77 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 78 79 /* Definitions for sampling clocks */ 80 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 81 { 82 .clk_rate = 0, 83 .tap = 0x00000300, 84 }, 85 }; 86 87 static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = { 88 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 89 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | 90 TMIO_MMC_HAVE_4TAP_HS400, 91 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 92 MMC_CAP_CMD23, 93 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 94 .bus_shift = 2, 95 .scc_offset = 0x1000, 96 .taps = rcar_gen3_scc_taps, 97 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 98 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 99 .max_blk_count = 0xffffffff, 100 .max_segs = 1, 101 }; 102 103 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 104 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 105 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 106 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 107 MMC_CAP_CMD23, 108 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 109 .bus_shift = 2, 110 .scc_offset = 0x1000, 111 .taps = rcar_gen3_scc_taps, 112 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 113 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 114 .max_blk_count = 0xffffffff, 115 .max_segs = 1, 116 }; 117 118 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 119 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, }, 120 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, }, 121 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 122 {}, 123 }; 124 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 125 126 static void 127 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 128 int addr, u64 val) 129 { 130 writeq(val, host->ctl + addr); 131 } 132 133 static void 134 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 135 { 136 struct renesas_sdhi *priv = host_to_priv(host); 137 138 if (!host->chan_tx || !host->chan_rx) 139 return; 140 141 if (!enable) 142 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 143 INFO1_CLEAR); 144 145 if (priv->dma_priv.enable) 146 priv->dma_priv.enable(host, enable); 147 } 148 149 static void 150 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 151 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 152 153 renesas_sdhi_internal_dmac_enable_dma(host, false); 154 155 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 156 RST_RESERVED_BITS & ~val); 157 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 158 RST_RESERVED_BITS | val); 159 160 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 161 162 renesas_sdhi_internal_dmac_enable_dma(host, true); 163 } 164 165 static void 166 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 167 struct renesas_sdhi *priv = host_to_priv(host); 168 169 tasklet_schedule(&priv->dma_priv.dma_complete); 170 } 171 172 static void 173 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 174 struct mmc_data *data) 175 { 176 struct scatterlist *sg = host->sg_ptr; 177 u32 dtran_mode = DTRAN_MODE_BUS_WID_TH | DTRAN_MODE_ADDR_MODE; 178 179 if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len, 180 mmc_get_dma_dir(data))) 181 goto force_pio; 182 183 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 184 if (!IS_ALIGNED(sg_dma_address(sg), 8)) 185 goto force_pio_with_unmap; 186 187 if (data->flags & MMC_DATA_READ) { 188 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 189 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 190 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 191 goto force_pio_with_unmap; 192 } else { 193 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 194 } 195 196 renesas_sdhi_internal_dmac_enable_dma(host, true); 197 198 /* set dma parameters */ 199 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 200 dtran_mode); 201 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 202 sg_dma_address(sg)); 203 204 return; 205 206 force_pio_with_unmap: 207 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data)); 208 209 force_pio: 210 host->force_pio = true; 211 renesas_sdhi_internal_dmac_enable_dma(host, false); 212 } 213 214 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 215 { 216 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 217 218 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 219 220 /* start the DMAC */ 221 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 222 DTRAN_CTRL_DM_START); 223 } 224 225 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 226 { 227 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 228 enum dma_data_direction dir; 229 230 spin_lock_irq(&host->lock); 231 232 if (!host->data) 233 goto out; 234 235 if (host->data->flags & MMC_DATA_READ) 236 dir = DMA_FROM_DEVICE; 237 else 238 dir = DMA_TO_DEVICE; 239 240 renesas_sdhi_internal_dmac_enable_dma(host, false); 241 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 242 243 if (dir == DMA_FROM_DEVICE) 244 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 245 246 tmio_mmc_do_data_irq(host); 247 out: 248 spin_unlock_irq(&host->lock); 249 } 250 251 static void 252 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 253 struct tmio_mmc_data *pdata) 254 { 255 struct renesas_sdhi *priv = host_to_priv(host); 256 257 /* Disable DMAC interrupts, we don't use them */ 258 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 259 INFO1_MASK_CLEAR); 260 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 261 INFO2_MASK_CLEAR); 262 263 /* Each value is set to non-zero to assume "enabling" each DMA */ 264 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 265 266 tasklet_init(&priv->dma_priv.dma_complete, 267 renesas_sdhi_internal_dmac_complete_tasklet_fn, 268 (unsigned long)host); 269 tasklet_init(&host->dma_issue, 270 renesas_sdhi_internal_dmac_issue_tasklet_fn, 271 (unsigned long)host); 272 } 273 274 static void 275 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 276 { 277 /* Each value is set to zero to assume "disabling" each DMA */ 278 host->chan_rx = host->chan_tx = NULL; 279 } 280 281 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 282 .start = renesas_sdhi_internal_dmac_start_dma, 283 .enable = renesas_sdhi_internal_dmac_enable_dma, 284 .request = renesas_sdhi_internal_dmac_request_dma, 285 .release = renesas_sdhi_internal_dmac_release_dma, 286 .abort = renesas_sdhi_internal_dmac_abort_dma, 287 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 288 }; 289 290 /* 291 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 292 * implementation as others may use a different implementation. 293 */ 294 static const struct soc_device_attribute gen3_soc_whitelist[] = { 295 /* specific ones */ 296 { .soc_id = "r8a7795", .revision = "ES1.*", 297 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 298 { .soc_id = "r8a7796", .revision = "ES1.0", 299 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 300 /* generic ones */ 301 { .soc_id = "r8a774a1" }, 302 { .soc_id = "r8a7795" }, 303 { .soc_id = "r8a7796" }, 304 { .soc_id = "r8a77965" }, 305 { .soc_id = "r8a77980" }, 306 { .soc_id = "r8a77995" }, 307 { /* sentinel */ } 308 }; 309 310 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 311 { 312 const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist); 313 314 if (!soc) 315 return -ENODEV; 316 317 global_flags |= (unsigned long)soc->data; 318 319 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 320 } 321 322 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 323 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 324 pm_runtime_force_resume) 325 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 326 tmio_mmc_host_runtime_resume, 327 NULL) 328 }; 329 330 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 331 .driver = { 332 .name = "renesas_sdhi_internal_dmac", 333 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 334 .of_match_table = renesas_sdhi_internal_dmac_of_match, 335 }, 336 .probe = renesas_sdhi_internal_dmac_probe, 337 .remove = renesas_sdhi_remove, 338 }; 339 340 module_platform_driver(renesas_internal_dmac_sdhi_driver); 341 342 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 343 MODULE_AUTHOR("Yoshihiro Shimoda"); 344 MODULE_LICENSE("GPL v2"); 345