1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-17 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io-64-nonatomic-hi-lo.h> 13 #include <linux/mfd/tmio.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pagemap.h> 18 #include <linux/scatterlist.h> 19 #include <linux/sys_soc.h> 20 21 #include "renesas_sdhi.h" 22 #include "tmio_mmc.h" 23 24 #define DM_CM_DTRAN_MODE 0x820 25 #define DM_CM_DTRAN_CTRL 0x828 26 #define DM_CM_RST 0x830 27 #define DM_CM_INFO1 0x840 28 #define DM_CM_INFO1_MASK 0x848 29 #define DM_CM_INFO2 0x850 30 #define DM_CM_INFO2_MASK 0x858 31 #define DM_DTRAN_ADDR 0x880 32 33 /* DM_CM_DTRAN_MODE */ 34 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 35 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 36 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 37 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address */ 38 39 /* DM_CM_DTRAN_CTRL */ 40 #define DTRAN_CTRL_DM_START BIT(0) 41 42 /* DM_CM_RST */ 43 #define RST_DTRANRST1 BIT(9) 44 #define RST_DTRANRST0 BIT(8) 45 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 46 47 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 48 #define INFO1_CLEAR 0 49 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 50 #define INFO1_DTRANEND1 BIT(17) 51 #define INFO1_DTRANEND0 BIT(16) 52 53 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 54 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 55 #define INFO2_DTRANERR1 BIT(17) 56 #define INFO2_DTRANERR0 BIT(16) 57 58 /* 59 * Specification of this driver: 60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 62 * need a custom accessor. 63 */ 64 65 static unsigned long global_flags; 66 /* 67 * Workaround for avoiding to use RX DMAC by multiple channels. 68 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 69 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 70 * stored into the system memory even if the DMAC interrupt happened. 71 * So, this driver then uses one RX DMAC channel only. 72 */ 73 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 74 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 75 76 /* Definitions for sampling clocks */ 77 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 78 { 79 .clk_rate = 0, 80 .tap = 0x00000300, 81 }, 82 }; 83 84 static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = { 85 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 86 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | 87 TMIO_MMC_HAVE_4TAP_HS400, 88 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 89 MMC_CAP_CMD23, 90 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 91 .bus_shift = 2, 92 .scc_offset = 0x1000, 93 .taps = rcar_gen3_scc_taps, 94 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 95 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 96 .max_blk_count = 0xffffffff, 97 .max_segs = 1, 98 }; 99 100 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 101 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 102 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 103 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 104 MMC_CAP_CMD23, 105 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 106 .bus_shift = 2, 107 .scc_offset = 0x1000, 108 .taps = rcar_gen3_scc_taps, 109 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 110 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 111 .max_blk_count = 0xffffffff, 112 .max_segs = 1, 113 }; 114 115 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 116 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, }, 117 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, }, 118 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 119 {}, 120 }; 121 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 122 123 static void 124 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 125 int addr, u64 val) 126 { 127 writeq(val, host->ctl + addr); 128 } 129 130 static void 131 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 132 { 133 struct renesas_sdhi *priv = host_to_priv(host); 134 135 if (!host->chan_tx || !host->chan_rx) 136 return; 137 138 if (!enable) 139 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 140 INFO1_CLEAR); 141 142 if (priv->dma_priv.enable) 143 priv->dma_priv.enable(host, enable); 144 } 145 146 static void 147 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 148 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 149 150 renesas_sdhi_internal_dmac_enable_dma(host, false); 151 152 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 153 RST_RESERVED_BITS & ~val); 154 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 155 RST_RESERVED_BITS | val); 156 157 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 158 159 renesas_sdhi_internal_dmac_enable_dma(host, true); 160 } 161 162 static void 163 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 164 struct renesas_sdhi *priv = host_to_priv(host); 165 166 tasklet_schedule(&priv->dma_priv.dma_complete); 167 } 168 169 static void 170 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 171 struct mmc_data *data) 172 { 173 struct scatterlist *sg = host->sg_ptr; 174 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH | DTRAN_MODE_ADDR_MODE; 175 176 if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len, 177 mmc_get_dma_dir(data))) 178 goto force_pio; 179 180 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 181 if (!IS_ALIGNED(sg_dma_address(sg), 8)) 182 goto force_pio_with_unmap; 183 184 if (data->flags & MMC_DATA_READ) { 185 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 186 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 187 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 188 goto force_pio_with_unmap; 189 } else { 190 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 191 } 192 193 renesas_sdhi_internal_dmac_enable_dma(host, true); 194 195 /* set dma parameters */ 196 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 197 dtran_mode); 198 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 199 sg_dma_address(sg)); 200 201 return; 202 203 force_pio_with_unmap: 204 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data)); 205 206 force_pio: 207 host->force_pio = true; 208 renesas_sdhi_internal_dmac_enable_dma(host, false); 209 } 210 211 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 212 { 213 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 214 215 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 216 217 /* start the DMAC */ 218 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 219 DTRAN_CTRL_DM_START); 220 } 221 222 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 223 { 224 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 225 enum dma_data_direction dir; 226 227 spin_lock_irq(&host->lock); 228 229 if (!host->data) 230 goto out; 231 232 if (host->data->flags & MMC_DATA_READ) 233 dir = DMA_FROM_DEVICE; 234 else 235 dir = DMA_TO_DEVICE; 236 237 renesas_sdhi_internal_dmac_enable_dma(host, false); 238 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 239 240 if (dir == DMA_FROM_DEVICE) 241 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 242 243 tmio_mmc_do_data_irq(host); 244 out: 245 spin_unlock_irq(&host->lock); 246 } 247 248 static void 249 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 250 struct tmio_mmc_data *pdata) 251 { 252 struct renesas_sdhi *priv = host_to_priv(host); 253 254 /* Disable DMAC interrupts, we don't use them */ 255 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 256 INFO1_MASK_CLEAR); 257 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 258 INFO2_MASK_CLEAR); 259 260 /* Each value is set to non-zero to assume "enabling" each DMA */ 261 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 262 263 tasklet_init(&priv->dma_priv.dma_complete, 264 renesas_sdhi_internal_dmac_complete_tasklet_fn, 265 (unsigned long)host); 266 tasklet_init(&host->dma_issue, 267 renesas_sdhi_internal_dmac_issue_tasklet_fn, 268 (unsigned long)host); 269 } 270 271 static void 272 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 273 { 274 /* Each value is set to zero to assume "disabling" each DMA */ 275 host->chan_rx = host->chan_tx = NULL; 276 } 277 278 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 279 .start = renesas_sdhi_internal_dmac_start_dma, 280 .enable = renesas_sdhi_internal_dmac_enable_dma, 281 .request = renesas_sdhi_internal_dmac_request_dma, 282 .release = renesas_sdhi_internal_dmac_release_dma, 283 .abort = renesas_sdhi_internal_dmac_abort_dma, 284 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 285 }; 286 287 /* 288 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 289 * implementation as others may use a different implementation. 290 */ 291 static const struct soc_device_attribute gen3_soc_whitelist[] = { 292 /* specific ones */ 293 { .soc_id = "r8a7795", .revision = "ES1.*", 294 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 295 { .soc_id = "r8a7796", .revision = "ES1.0", 296 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 297 /* generic ones */ 298 { .soc_id = "r8a774a1" }, 299 { .soc_id = "r8a7795" }, 300 { .soc_id = "r8a7796" }, 301 { .soc_id = "r8a77965" }, 302 { .soc_id = "r8a77970" }, 303 { .soc_id = "r8a77980" }, 304 { .soc_id = "r8a77995" }, 305 { /* sentinel */ } 306 }; 307 308 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 309 { 310 const struct soc_device_attribute *soc = soc_device_match(gen3_soc_whitelist); 311 312 if (!soc) 313 return -ENODEV; 314 315 global_flags |= (unsigned long)soc->data; 316 317 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 318 } 319 320 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 321 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 322 pm_runtime_force_resume) 323 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 324 tmio_mmc_host_runtime_resume, 325 NULL) 326 }; 327 328 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 329 .driver = { 330 .name = "renesas_sdhi_internal_dmac", 331 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 332 .of_match_table = renesas_sdhi_internal_dmac_of_match, 333 }, 334 .probe = renesas_sdhi_internal_dmac_probe, 335 .remove = renesas_sdhi_remove, 336 }; 337 338 module_platform_driver(renesas_internal_dmac_sdhi_driver); 339 340 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 341 MODULE_AUTHOR("Yoshihiro Shimoda"); 342 MODULE_LICENSE("GPL v2"); 343