1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-17 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io-64-nonatomic-hi-lo.h> 13 #include <linux/mfd/tmio.h> 14 #include <linux/mmc/host.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pagemap.h> 18 #include <linux/scatterlist.h> 19 #include <linux/sys_soc.h> 20 21 #include "renesas_sdhi.h" 22 #include "tmio_mmc.h" 23 24 #define DM_CM_DTRAN_MODE 0x820 25 #define DM_CM_DTRAN_CTRL 0x828 26 #define DM_CM_RST 0x830 27 #define DM_CM_INFO1 0x840 28 #define DM_CM_INFO1_MASK 0x848 29 #define DM_CM_INFO2 0x850 30 #define DM_CM_INFO2_MASK 0x858 31 #define DM_DTRAN_ADDR 0x880 32 33 /* DM_CM_DTRAN_MODE */ 34 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 35 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 36 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 37 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 38 39 /* DM_CM_DTRAN_CTRL */ 40 #define DTRAN_CTRL_DM_START BIT(0) 41 42 /* DM_CM_RST */ 43 #define RST_DTRANRST1 BIT(9) 44 #define RST_DTRANRST0 BIT(8) 45 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 46 47 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 48 #define INFO1_CLEAR 0 49 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 50 #define INFO1_DTRANEND1 BIT(17) 51 #define INFO1_DTRANEND0 BIT(16) 52 53 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 54 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 55 #define INFO2_DTRANERR1 BIT(17) 56 #define INFO2_DTRANERR0 BIT(16) 57 58 /* 59 * Specification of this driver: 60 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 61 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 62 * need a custom accessor. 63 */ 64 65 static unsigned long global_flags; 66 /* 67 * Workaround for avoiding to use RX DMAC by multiple channels. 68 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 69 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 70 * stored into the system memory even if the DMAC interrupt happened. 71 * So, this driver then uses one RX DMAC channel only. 72 */ 73 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 74 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 75 76 /* RZ/A2 does not have the ADRR_MODE bit */ 77 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2 78 79 /* Definitions for sampling clocks */ 80 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 81 { 82 .clk_rate = 0, 83 .tap = 0x00000300, 84 }, 85 }; 86 87 static const struct renesas_sdhi_of_data of_rza2_compatible = { 88 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 89 TMIO_MMC_HAVE_CBSY, 90 .tmio_ocr_mask = MMC_VDD_32_33, 91 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 92 MMC_CAP_CMD23, 93 .bus_shift = 2, 94 .scc_offset = 0 - 0x1000, 95 .taps = rcar_gen3_scc_taps, 96 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 97 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 98 .max_blk_count = 0xffffffff, 99 .max_segs = 1, 100 }; 101 102 static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = { 103 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 104 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | 105 TMIO_MMC_HAVE_4TAP_HS400, 106 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 107 MMC_CAP_CMD23, 108 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 109 .bus_shift = 2, 110 .scc_offset = 0x1000, 111 .taps = rcar_gen3_scc_taps, 112 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 113 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 114 .max_blk_count = 0xffffffff, 115 .max_segs = 1, 116 }; 117 118 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = { 119 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 120 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 121 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 122 MMC_CAP_CMD23, 123 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT, 124 .bus_shift = 2, 125 .scc_offset = 0x1000, 126 .taps = rcar_gen3_scc_taps, 127 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 128 /* DMAC can handle 0xffffffff blk count but only 1 segment */ 129 .max_blk_count = 0xffffffff, 130 .max_segs = 1, 131 }; 132 133 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 134 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 135 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 136 { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, }, 137 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, }, 138 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 139 {}, 140 }; 141 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 142 143 static void 144 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 145 int addr, u64 val) 146 { 147 writeq(val, host->ctl + addr); 148 } 149 150 static void 151 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 152 { 153 struct renesas_sdhi *priv = host_to_priv(host); 154 155 if (!host->chan_tx || !host->chan_rx) 156 return; 157 158 if (!enable) 159 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 160 INFO1_CLEAR); 161 162 if (priv->dma_priv.enable) 163 priv->dma_priv.enable(host, enable); 164 } 165 166 static void 167 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 168 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 169 170 renesas_sdhi_internal_dmac_enable_dma(host, false); 171 172 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 173 RST_RESERVED_BITS & ~val); 174 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 175 RST_RESERVED_BITS | val); 176 177 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 178 179 renesas_sdhi_internal_dmac_enable_dma(host, true); 180 } 181 182 static void 183 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 184 struct renesas_sdhi *priv = host_to_priv(host); 185 186 tasklet_schedule(&priv->dma_priv.dma_complete); 187 } 188 189 static void 190 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 191 struct mmc_data *data) 192 { 193 struct scatterlist *sg = host->sg_ptr; 194 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 195 196 if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags)) 197 dtran_mode |= DTRAN_MODE_ADDR_MODE; 198 199 if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len, 200 mmc_get_dma_dir(data))) 201 goto force_pio; 202 203 /* This DMAC cannot handle if buffer is not 8-bytes alignment */ 204 if (!IS_ALIGNED(sg_dma_address(sg), 8)) 205 goto force_pio_with_unmap; 206 207 if (data->flags & MMC_DATA_READ) { 208 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 209 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 210 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 211 goto force_pio_with_unmap; 212 } else { 213 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 214 } 215 216 renesas_sdhi_internal_dmac_enable_dma(host, true); 217 218 /* set dma parameters */ 219 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 220 dtran_mode); 221 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 222 sg_dma_address(sg)); 223 224 host->dma_on = true; 225 226 return; 227 228 force_pio_with_unmap: 229 dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data)); 230 231 force_pio: 232 renesas_sdhi_internal_dmac_enable_dma(host, false); 233 } 234 235 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 236 { 237 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 238 239 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 240 241 /* start the DMAC */ 242 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 243 DTRAN_CTRL_DM_START); 244 } 245 246 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 247 { 248 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 249 enum dma_data_direction dir; 250 251 spin_lock_irq(&host->lock); 252 253 if (!host->data) 254 goto out; 255 256 if (host->data->flags & MMC_DATA_READ) 257 dir = DMA_FROM_DEVICE; 258 else 259 dir = DMA_TO_DEVICE; 260 261 renesas_sdhi_internal_dmac_enable_dma(host, false); 262 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir); 263 264 if (dir == DMA_FROM_DEVICE) 265 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 266 267 tmio_mmc_do_data_irq(host); 268 out: 269 spin_unlock_irq(&host->lock); 270 } 271 272 static void 273 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 274 struct tmio_mmc_data *pdata) 275 { 276 struct renesas_sdhi *priv = host_to_priv(host); 277 278 /* Disable DMAC interrupts, we don't use them */ 279 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 280 INFO1_MASK_CLEAR); 281 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 282 INFO2_MASK_CLEAR); 283 284 /* Each value is set to non-zero to assume "enabling" each DMA */ 285 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 286 287 tasklet_init(&priv->dma_priv.dma_complete, 288 renesas_sdhi_internal_dmac_complete_tasklet_fn, 289 (unsigned long)host); 290 tasklet_init(&host->dma_issue, 291 renesas_sdhi_internal_dmac_issue_tasklet_fn, 292 (unsigned long)host); 293 } 294 295 static void 296 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 297 { 298 /* Each value is set to zero to assume "disabling" each DMA */ 299 host->chan_rx = host->chan_tx = NULL; 300 } 301 302 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 303 .start = renesas_sdhi_internal_dmac_start_dma, 304 .enable = renesas_sdhi_internal_dmac_enable_dma, 305 .request = renesas_sdhi_internal_dmac_request_dma, 306 .release = renesas_sdhi_internal_dmac_release_dma, 307 .abort = renesas_sdhi_internal_dmac_abort_dma, 308 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 309 }; 310 311 /* 312 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 313 * implementation as others may use a different implementation. 314 */ 315 static const struct soc_device_attribute soc_whitelist[] = { 316 /* specific ones */ 317 { .soc_id = "r7s9210", 318 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) }, 319 { .soc_id = "r8a7795", .revision = "ES1.*", 320 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 321 { .soc_id = "r8a7796", .revision = "ES1.0", 322 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 323 /* generic ones */ 324 { .soc_id = "r8a774a1" }, 325 { .soc_id = "r8a77470" }, 326 { .soc_id = "r8a7795" }, 327 { .soc_id = "r8a7796" }, 328 { .soc_id = "r8a77965" }, 329 { .soc_id = "r8a77970" }, 330 { .soc_id = "r8a77980" }, 331 { .soc_id = "r8a77995" }, 332 { /* sentinel */ } 333 }; 334 335 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 336 { 337 const struct soc_device_attribute *soc = soc_device_match(soc_whitelist); 338 struct device *dev = &pdev->dev; 339 340 if (!soc) 341 return -ENODEV; 342 343 global_flags |= (unsigned long)soc->data; 344 345 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL); 346 if (!dev->dma_parms) 347 return -ENOMEM; 348 349 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 350 dma_set_max_seg_size(dev, 0xffffffff); 351 352 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops); 353 } 354 355 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 356 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 357 pm_runtime_force_resume) 358 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 359 tmio_mmc_host_runtime_resume, 360 NULL) 361 }; 362 363 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 364 .driver = { 365 .name = "renesas_sdhi_internal_dmac", 366 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 367 .of_match_table = renesas_sdhi_internal_dmac_of_match, 368 }, 369 .probe = renesas_sdhi_internal_dmac_probe, 370 .remove = renesas_sdhi_remove, 371 }; 372 373 module_platform_driver(renesas_internal_dmac_sdhi_driver); 374 375 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 376 MODULE_AUTHOR("Yoshihiro Shimoda"); 377 MODULE_LICENSE("GPL v2"); 378