arm64: dts: imx8mn: Add sound-dai-cells to micfil node

[ Upstream commit db1925454a2e7cadcac8756442ca7c3198332336 ]

Per the DT bindings, the micfil node should have a sound-dai-cells
entry.

Fixes:

arm64: dts: imx8mn: Add sound-dai-cells to micfil node

[ Upstream commit db1925454a2e7cadcac8756442ca7c3198332336 ]

Per the DT bindings, the micfil node should have a sound-dai-cells
entry.

Fixes: cca69ef6eba5 ("arm64: dts: imx8mn: Add support for micfil")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration

The CSI1 PHY reference clock are limited to 125 MHz according to:
i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/202

arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration

The CSI1 PHY reference clock are limited to 125 MHz according to:
i.MX 8M Nano Applications Processor Reference Manual, Rev. 2, 07/2022
Table 5-1. Clock Root Table (continued) / page 319
Slice Index n = 123 .

Currently those IMX8MN_CLK_CSI1_PHY_REF clock are configured to be
fed directly from 1 GHz PLL2 , which overclocks them . Instead, drop
the configuration altogether, which defaults the clock to 24 MHz REF
clock input, which for the PHY reference clock is just fine.

Fixes: ae9279f301b5 ("arm64: dts: imx8mn: Add CSI and ISI Nodes")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Add CSI and ISI Nodes

The CSI in the imx8mn is the same as what is used in the imx8mm,
but it's routed to the ISI on the Nano. Add both the ISI and CSI
nodes, and pointing them t

arm64: dts: imx8mn: Add CSI and ISI Nodes

The CSI in the imx8mn is the same as what is used in the imx8mm,
but it's routed to the ISI on the Nano. Add both the ISI and CSI
nodes, and pointing them to each other. Since the CSI capture is
dependent on an attached camera, mark both ISI and CSI as
disabled by default.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Fix video clock parents

There are a few clocks whose parents are set in mipi_dsi
and mxsfb nodes, but these clocks are used by the disp_blk_ctrl
power domain which may cause an i

arm64: dts: imx8mn: Fix video clock parents

There are a few clocks whose parents are set in mipi_dsi
and mxsfb nodes, but these clocks are used by the disp_blk_ctrl
power domain which may cause an issue when re-parenting, resuling
in a disp_pixel clock having the wrong parent and wrong rate.

Fix this by moving the assigned-clock-parents as associate clock
assignments to the power-domain node to setup these clocks before
they are enabled.

Fixes: d825fb6455d5 ("arm64: dts: imx8mn: Add display pipeline components")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Add display pipeline components

Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano.
This makes the DSI display pipeline available on this SoC.

Signed-off-by: Marek V

arm64: dts: imx8mn: Add display pipeline components

Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano.
This makes the DSI display pipeline available on this SoC.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: update usb compatible

Update usb compatible per binding doc

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20230322052504.2629429-5-peng.fan@oss.nxp.

arm64: dts: imx8mn: update usb compatible

Update usb compatible per binding doc

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20230322052504.2629429-5-peng.fan@oss.nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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arm64: dts: imx8mn: specify #sound-dai-cells for SAI nodes

Add #sound-dai-cells properties to SAI nodes.

Reviewed-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

arm64: dts: imx8mn: specify #sound-dai-cells for SAI nodes

Add #sound-dai-cells properties to SAI nodes.

Reviewed-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Fixes: 9e9860069725 ("arm64: dts: imx8mn: Add SAI nodes")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: update iomuxc-gpr node name

It is better use syscon for IOMUXC GPR, since it contains various
bits for system control

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Mar

arm64: dts: imx8mn: update iomuxc-gpr node name

It is better use syscon for IOMUXC GPR, since it contains various
bits for system control

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Drop dma-apb interrupt-names

Drop "interrupt-names" property, since it is broken. The drivers/dma/mxs-dma.c
in Linux kernel does not use it, the property contains duplicate array

arm64: dts: imx8mn: Drop dma-apb interrupt-names

Drop "interrupt-names" property, since it is broken. The drivers/dma/mxs-dma.c
in Linux kernel does not use it, the property contains duplicate array entries
in existing DTs, and even malformed entries (gmpi, should have been gpmi). Get
rid of that optional property altogether.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP

The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values

arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP

The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.

The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8m: Document the fuse address calculation

The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to fi

arm64: dts: imx8m: Document the fuse address calculation

The mapping from OCOTP reg DT property to Fusemap Descriptions Table in
the datasheet is often unclear. Add a comment to make it easier to find
out how it works. No functional change.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8m: Align SoC unique ID node unit address

Align the SoC unique ID DT node unit address with its reg property.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fixes: cbff23797fa1 ("arm64: dt

arm64: dts: imx8m: Align SoC unique ID node unit address

Align the SoC unique ID DT node unit address with its reg property.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fixes: cbff23797fa1 ("arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: Update cache properties for freescale

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and S

arm64: dts: Update cache properties for freescale

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Chester Lin <clin@suse.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Fix NAND controller size-cells

The NAND controller size-cells should be 0 per DT bindings.
Fix the following warning produces by DT bindings check:
"
nand-controller@33002000: #s

arm64: dts: imx8mn: Fix NAND controller size-cells

The NAND controller size-cells should be 0 per DT bindings.
Fix the following warning produces by DT bindings check:
"
nand-controller@33002000: #size-cells:0:0: 0 was expected
nand-controller@33002000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected)
"

Fixes: 6c3debcbae47a ("arm64: dts: freescale: Add i.MX8MN dtsi support")
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Correct the usb power domain

pgc_otg1 is actual the power domain of usb PHY, usb controller
is in hsio power domain, and pgc_otg1 is required to be powered
up to detect usb remot

arm64: dts: imx8mn: Correct the usb power domain

pgc_otg1 is actual the power domain of usb PHY, usb controller
is in hsio power domain, and pgc_otg1 is required to be powered
up to detect usb remote wakeup, so move the pgc_otg1 power domain
to the usb phy node.

Fixes: ea2b5af58ab2 ("arm64: dts: imx8mn: put USB controller into power-domains")
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: remove otg1 power domain dependency on hsio

pgc_otg1 is an independent power domain of hsio, it's for usb phy,
so remove hsio power domain from its node.

Fixes: 8b8ebec67360 ("a

arm64: dts: imx8mn: remove otg1 power domain dependency on hsio

pgc_otg1 is an independent power domain of hsio, it's for usb phy,
so remove hsio power domain from its node.

Fixes: 8b8ebec67360 ("arm64: dts: imx8mn: add GPC node")
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8m: align anatop with bindings

The CCM ANALOG module is used for generate PLLs, align the node
with DT bindings

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <s

arm64: dts: imx8m: align anatop with bindings

The CCM ANALOG module is used for generate PLLs, align the node
with DT bindings

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: remove GPU power domain reset

The PGC (power gating controller) already handles the reset for the
GPUMIX power domain. By specifying it within the device tree the reset
it issued

arm64: dts: imx8mn: remove GPU power domain reset

The PGC (power gating controller) already handles the reset for the
GPUMIX power domain. By specifying it within the device tree the reset
it issued a 2nd time. This confuses the hardware during power up and
sporadically hangs the SoC. Fix this by removing the reset property and
let the hardware handle the reset.

Fixes: 9a0f3b157e22e ("arm64: dts: imx8mn: Enable GPU")
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8m: Pass a label to the soc node

Pass a label to the 'soc' node to make it easier to reference
it from other devicetree files.

U-Boot, for example usually needs to access the AIPS no

arm64: dts: imx8m: Pass a label to the soc node

Pass a label to the 'soc' node to make it easier to reference
it from other devicetree files.

U-Boot, for example usually needs to access the AIPS node to
pass U-Boot-specific properties.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8m: Disable job ring 0 nodes

Now that the JR0 reservation is done in both upstream (v2.7) and
downstream (NXP lf_v2.4) TF-A versions, the kernel fails to initialize
the job ring 0:

arm64: dts: imx8m: Disable job ring 0 nodes

Now that the JR0 reservation is done in both upstream (v2.7) and
downstream (NXP lf_v2.4) TF-A versions, the kernel fails to initialize
the job ring 0:

# dmesg | grep jr
caam_jr 30901000.jr: failed to flush job ring 0
caam_jr: probe of 30901000.jr failed with error -5

Disable the sec_jr0 nodes by default to avoid the caam_jr probe error.

Suggested-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: fsl: adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DT

arm64: dts: fsl: adjust whitespace around '='

Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dt: imx8mn: support pwm polarity inversion

The i.MX8M Nano has the same PWM IP as i.MX6 / i.MX7. This IP
and the driver supporting pwm polarity inversion. Switch CPU
device tree fragment to u

arm64: dt: imx8mn: support pwm polarity inversion

The i.MX8M Nano has the same PWM IP as i.MX6 / i.MX7. This IP
and the driver supporting pwm polarity inversion. Switch CPU
device tree fragment to use 3 pwm-cells.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Enable HS400-ES

The SDHC controller in the imx8mn has the same controller
as the imx8mm which supports HS400-ES. Change the compatible
fallback to imx8mm to enable it, but keep t

arm64: dts: imx8mn: Enable HS400-ES

The SDHC controller in the imx8mn has the same controller
as the imx8mm which supports HS400-ES. Change the compatible
fallback to imx8mm to enable it, but keep the imx7d-usdhc
to prevent breaking backwards compatibility.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Fix SAI nodes

The most specific compatible string element should be "fsl,imx8mn-sai"
on i.MX8M Nano, fix it from current "fsl,imx8mm-sai" (two Ms, likely
due to copy-paste error

arm64: dts: imx8mn: Fix SAI nodes

The most specific compatible string element should be "fsl,imx8mn-sai"
on i.MX8M Nano, fix it from current "fsl,imx8mm-sai" (two Ms, likely
due to copy-paste error from i.MX8M Mini).

Fixes: 9e9860069725f ("arm64: dts: imx8mn: Add SAI nodes")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Adam Ford <aford173@gmail.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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arm64: dts: imx8mn: Enable GPU

The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as:

etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203

Signed-off-by: Adam Ford <aford173@g

arm64: dts: imx8mn: Enable GPU

The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as:

etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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