1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; 66 clocks = <&clk IMX8MN_CLK_ARM>; 67 enable-method = "psci"; 68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 75 operating-points-v2 = <&a53_opp_table>; 76 nvmem-cells = <&cpu_speed_grade>; 77 nvmem-cell-names = "speed_grade"; 78 cpu-idle-states = <&cpu_pd_wait>; 79 #cooling-cells = <2>; 80 }; 81 82 A53_1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x1>; 86 clock-latency = <61036>; 87 clocks = <&clk IMX8MN_CLK_ARM>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 cpu-idle-states = <&cpu_pd_wait>; 98 #cooling-cells = <2>; 99 }; 100 101 A53_2: cpu@2 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x2>; 105 clock-latency = <61036>; 106 clocks = <&clk IMX8MN_CLK_ARM>; 107 enable-method = "psci"; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&A53_L2>; 115 operating-points-v2 = <&a53_opp_table>; 116 cpu-idle-states = <&cpu_pd_wait>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_3: cpu@3 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x3>; 124 clock-latency = <61036>; 125 clocks = <&clk IMX8MN_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 cpu-idle-states = <&cpu_pd_wait>; 136 #cooling-cells = <2>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-level = <2>; 142 cache-unified; 143 cache-size = <0x80000>; 144 cache-line-size = <64>; 145 cache-sets = <512>; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-1200000000 { 154 opp-hz = /bits/ 64 <1200000000>; 155 opp-microvolt = <850000>; 156 opp-supported-hw = <0xb00>, <0x7>; 157 clock-latency-ns = <150000>; 158 opp-suspend; 159 }; 160 161 opp-1400000000 { 162 opp-hz = /bits/ 64 <1400000000>; 163 opp-microvolt = <950000>; 164 opp-supported-hw = <0x300>, <0x7>; 165 clock-latency-ns = <150000>; 166 opp-suspend; 167 }; 168 169 opp-1500000000 { 170 opp-hz = /bits/ 64 <1500000000>; 171 opp-microvolt = <1000000>; 172 opp-supported-hw = <0x100>, <0x3>; 173 clock-latency-ns = <150000>; 174 opp-suspend; 175 }; 176 }; 177 178 osc_32k: clock-osc-32k { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency = <32768>; 182 clock-output-names = "osc_32k"; 183 }; 184 185 osc_24m: clock-osc-24m { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <24000000>; 189 clock-output-names = "osc_24m"; 190 }; 191 192 clk_ext1: clock-ext1 { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <133000000>; 196 clock-output-names = "clk_ext1"; 197 }; 198 199 clk_ext2: clock-ext2 { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <133000000>; 203 clock-output-names = "clk_ext2"; 204 }; 205 206 clk_ext3: clock-ext3 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <133000000>; 210 clock-output-names = "clk_ext3"; 211 }; 212 213 clk_ext4: clock-ext4 { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 clock-frequency = <133000000>; 217 clock-output-names = "clk_ext4"; 218 }; 219 220 pmu { 221 compatible = "arm,cortex-a53-pmu"; 222 interrupts = <GIC_PPI 7 223 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 224 }; 225 226 psci { 227 compatible = "arm,psci-1.0"; 228 method = "smc"; 229 }; 230 231 thermal-zones { 232 cpu-thermal { 233 polling-delay-passive = <250>; 234 polling-delay = <2000>; 235 thermal-sensors = <&tmu>; 236 trips { 237 cpu_alert0: trip0 { 238 temperature = <85000>; 239 hysteresis = <2000>; 240 type = "passive"; 241 }; 242 243 cpu_crit0: trip1 { 244 temperature = <95000>; 245 hysteresis = <2000>; 246 type = "critical"; 247 }; 248 }; 249 250 cooling-maps { 251 map0 { 252 trip = <&cpu_alert0>; 253 cooling-device = 254 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 255 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 256 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 257 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 258 }; 259 }; 260 }; 261 }; 262 263 timer { 264 compatible = "arm,armv8-timer"; 265 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 266 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 267 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 268 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 269 clock-frequency = <8000000>; 270 arm,no-tick-in-suspend; 271 }; 272 273 soc: soc@0 { 274 compatible = "fsl,imx8mn-soc", "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges = <0x0 0x0 0x0 0x3e000000>; 278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 279 nvmem-cells = <&imx8mn_uid>; 280 nvmem-cell-names = "soc_unique_id"; 281 282 aips1: bus@30000000 { 283 compatible = "fsl,aips-bus", "simple-bus"; 284 reg = <0x30000000 0x400000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 spba2: spba-bus@30000000 { 290 compatible = "fsl,spba-bus", "simple-bus"; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 reg = <0x30000000 0x100000>; 294 ranges; 295 296 sai2: sai@30020000 { 297 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 298 reg = <0x30020000 0x10000>; 299 #sound-dai-cells = <0>; 300 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 302 <&clk IMX8MN_CLK_DUMMY>, 303 <&clk IMX8MN_CLK_SAI2_ROOT>, 304 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 305 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 306 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 307 dma-names = "rx", "tx"; 308 status = "disabled"; 309 }; 310 311 sai3: sai@30030000 { 312 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 313 reg = <0x30030000 0x10000>; 314 #sound-dai-cells = <0>; 315 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 317 <&clk IMX8MN_CLK_DUMMY>, 318 <&clk IMX8MN_CLK_SAI3_ROOT>, 319 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 320 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 321 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 }; 325 326 sai5: sai@30050000 { 327 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 328 reg = <0x30050000 0x10000>; 329 #sound-dai-cells = <0>; 330 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 332 <&clk IMX8MN_CLK_DUMMY>, 333 <&clk IMX8MN_CLK_SAI5_ROOT>, 334 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 335 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 336 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 337 dma-names = "rx", "tx"; 338 fsl,shared-interrupt; 339 fsl,dataline = <0 0xf 0xf>; 340 status = "disabled"; 341 }; 342 343 sai6: sai@30060000 { 344 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 345 reg = <0x30060000 0x10000>; 346 #sound-dai-cells = <0>; 347 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 349 <&clk IMX8MN_CLK_DUMMY>, 350 <&clk IMX8MN_CLK_SAI6_ROOT>, 351 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 352 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 353 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 354 dma-names = "rx", "tx"; 355 status = "disabled"; 356 }; 357 358 micfil: audio-controller@30080000 { 359 compatible = "fsl,imx8mm-micfil"; 360 reg = <0x30080000 0x10000>; 361 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 366 <&clk IMX8MN_CLK_PDM_ROOT>, 367 <&clk IMX8MN_AUDIO_PLL1_OUT>, 368 <&clk IMX8MN_AUDIO_PLL2_OUT>, 369 <&clk IMX8MN_CLK_EXT3>; 370 clock-names = "ipg_clk", "ipg_clk_app", 371 "pll8k", "pll11k", "clkext3"; 372 dmas = <&sdma2 24 25 0x80000000>; 373 dma-names = "rx"; 374 #sound-dai-cells = <0>; 375 status = "disabled"; 376 }; 377 378 spdif1: spdif@30090000 { 379 compatible = "fsl,imx35-spdif"; 380 reg = <0x30090000 0x10000>; 381 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 383 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 384 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 386 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 387 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 388 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 389 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 390 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 391 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 392 clock-names = "core", "rxtx0", 393 "rxtx1", "rxtx2", 394 "rxtx3", "rxtx4", 395 "rxtx5", "rxtx6", 396 "rxtx7", "spba"; 397 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 398 dma-names = "rx", "tx"; 399 status = "disabled"; 400 }; 401 402 sai7: sai@300b0000 { 403 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 404 reg = <0x300b0000 0x10000>; 405 #sound-dai-cells = <0>; 406 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 408 <&clk IMX8MN_CLK_DUMMY>, 409 <&clk IMX8MN_CLK_SAI7_ROOT>, 410 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 411 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 412 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 413 dma-names = "rx", "tx"; 414 status = "disabled"; 415 }; 416 417 easrc: easrc@300c0000 { 418 compatible = "fsl,imx8mn-easrc"; 419 reg = <0x300c0000 0x10000>; 420 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 422 clock-names = "mem"; 423 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 424 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 425 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 426 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 427 dma-names = "ctx0_rx", "ctx0_tx", 428 "ctx1_rx", "ctx1_tx", 429 "ctx2_rx", "ctx2_tx", 430 "ctx3_rx", "ctx3_tx"; 431 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 432 fsl,asrc-rate = <8000>; 433 fsl,asrc-format = <2>; 434 status = "disabled"; 435 }; 436 }; 437 438 gpio1: gpio@30200000 { 439 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 440 reg = <0x30200000 0x10000>; 441 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 gpio-ranges = <&iomuxc 0 10 30>; 449 }; 450 451 gpio2: gpio@30210000 { 452 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 453 reg = <0x30210000 0x10000>; 454 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 gpio-ranges = <&iomuxc 0 40 21>; 462 }; 463 464 gpio3: gpio@30220000 { 465 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 466 reg = <0x30220000 0x10000>; 467 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 gpio-ranges = <&iomuxc 0 61 26>; 475 }; 476 477 gpio4: gpio@30230000 { 478 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 479 reg = <0x30230000 0x10000>; 480 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 gpio-ranges = <&iomuxc 21 108 11>; 488 }; 489 490 gpio5: gpio@30240000 { 491 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 492 reg = <0x30240000 0x10000>; 493 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 gpio-ranges = <&iomuxc 0 119 30>; 501 }; 502 503 tmu: tmu@30260000 { 504 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 505 reg = <0x30260000 0x10000>; 506 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 507 nvmem-cells = <&tmu_calib>; 508 nvmem-cell-names = "calib"; 509 #thermal-sensor-cells = <0>; 510 }; 511 512 wdog1: watchdog@30280000 { 513 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 514 reg = <0x30280000 0x10000>; 515 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 517 status = "disabled"; 518 }; 519 520 wdog2: watchdog@30290000 { 521 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 522 reg = <0x30290000 0x10000>; 523 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 525 status = "disabled"; 526 }; 527 528 wdog3: watchdog@302a0000 { 529 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 530 reg = <0x302a0000 0x10000>; 531 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 533 status = "disabled"; 534 }; 535 536 sdma3: dma-controller@302b0000 { 537 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 538 reg = <0x302b0000 0x10000>; 539 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 541 <&clk IMX8MN_CLK_SDMA3_ROOT>; 542 clock-names = "ipg", "ahb"; 543 #dma-cells = <3>; 544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 545 }; 546 547 sdma2: dma-controller@302c0000 { 548 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 549 reg = <0x302c0000 0x10000>; 550 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 552 <&clk IMX8MN_CLK_SDMA2_ROOT>; 553 clock-names = "ipg", "ahb"; 554 #dma-cells = <3>; 555 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 556 }; 557 558 iomuxc: pinctrl@30330000 { 559 compatible = "fsl,imx8mn-iomuxc"; 560 reg = <0x30330000 0x10000>; 561 }; 562 563 gpr: syscon@30340000 { 564 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 565 reg = <0x30340000 0x10000>; 566 }; 567 568 ocotp: efuse@30350000 { 569 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 570 reg = <0x30350000 0x10000>; 571 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 575 /* 576 * The register address below maps to the MX8M 577 * Fusemap Description Table entries this way. 578 * Assuming 579 * reg = <ADDR SIZE>; 580 * then 581 * Fuse Address = (ADDR * 4) + 0x400 582 * Note that if SIZE is greater than 4, then 583 * each subsequent fuse is located at offset 584 * +0x10 in Fusemap Description Table (e.g. 585 * reg = <0x4 0x8> describes fuses 0x410 and 586 * 0x420). 587 */ 588 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ 589 reg = <0x4 0x8>; 590 }; 591 592 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 593 reg = <0x10 4>; 594 }; 595 596 tmu_calib: calib@3c { /* 0x4f0 */ 597 reg = <0x3c 4>; 598 }; 599 600 fec_mac_address: mac-address@90 { /* 0x640 */ 601 reg = <0x90 6>; 602 }; 603 }; 604 605 anatop: clock-controller@30360000 { 606 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; 607 reg = <0x30360000 0x10000>; 608 #clock-cells = <1>; 609 }; 610 611 snvs: snvs@30370000 { 612 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 613 reg = <0x30370000 0x10000>; 614 615 snvs_rtc: snvs-rtc-lp { 616 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 617 regmap = <&snvs>; 618 offset = <0x34>; 619 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 622 clock-names = "snvs-rtc"; 623 }; 624 625 snvs_pwrkey: snvs-powerkey { 626 compatible = "fsl,sec-v4.0-pwrkey"; 627 regmap = <&snvs>; 628 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 630 clock-names = "snvs-pwrkey"; 631 linux,keycode = <KEY_POWER>; 632 wakeup-source; 633 status = "disabled"; 634 }; 635 }; 636 637 clk: clock-controller@30380000 { 638 compatible = "fsl,imx8mn-ccm"; 639 reg = <0x30380000 0x10000>; 640 #clock-cells = <1>; 641 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 642 <&clk_ext3>, <&clk_ext4>; 643 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 644 "clk_ext3", "clk_ext4"; 645 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 646 <&clk IMX8MN_CLK_A53_CORE>, 647 <&clk IMX8MN_CLK_NOC>, 648 <&clk IMX8MN_CLK_AUDIO_AHB>, 649 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 650 <&clk IMX8MN_SYS_PLL3>, 651 <&clk IMX8MN_AUDIO_PLL1>, 652 <&clk IMX8MN_AUDIO_PLL2>; 653 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 654 <&clk IMX8MN_ARM_PLL_OUT>, 655 <&clk IMX8MN_SYS_PLL3_OUT>, 656 <&clk IMX8MN_SYS_PLL1_800M>; 657 assigned-clock-rates = <0>, <0>, <0>, 658 <400000000>, 659 <400000000>, 660 <600000000>, 661 <393216000>, 662 <361267200>; 663 }; 664 665 src: reset-controller@30390000 { 666 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 667 reg = <0x30390000 0x10000>; 668 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 669 #reset-cells = <1>; 670 }; 671 672 gpc: gpc@303a0000 { 673 compatible = "fsl,imx8mn-gpc"; 674 reg = <0x303a0000 0x10000>; 675 interrupt-parent = <&gic>; 676 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 677 678 pgc { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 682 pgc_hsiomix: power-domain@0 { 683 #power-domain-cells = <0>; 684 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 685 clocks = <&clk IMX8MN_CLK_USB_BUS>; 686 }; 687 688 pgc_otg1: power-domain@1 { 689 #power-domain-cells = <0>; 690 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 691 }; 692 693 pgc_gpumix: power-domain@2 { 694 #power-domain-cells = <0>; 695 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 696 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 697 <&clk IMX8MN_CLK_GPU_SHADER>, 698 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 699 <&clk IMX8MN_CLK_GPU_AHB>; 700 }; 701 702 pgc_dispmix: power-domain@3 { 703 #power-domain-cells = <0>; 704 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 705 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 706 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 707 }; 708 709 pgc_mipi: power-domain@4 { 710 #power-domain-cells = <0>; 711 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 712 power-domains = <&pgc_dispmix>; 713 }; 714 }; 715 }; 716 }; 717 718 aips2: bus@30400000 { 719 compatible = "fsl,aips-bus", "simple-bus"; 720 reg = <0x30400000 0x400000>; 721 #address-cells = <1>; 722 #size-cells = <1>; 723 ranges; 724 725 pwm1: pwm@30660000 { 726 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 727 reg = <0x30660000 0x10000>; 728 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 730 <&clk IMX8MN_CLK_PWM1_ROOT>; 731 clock-names = "ipg", "per"; 732 #pwm-cells = <3>; 733 status = "disabled"; 734 }; 735 736 pwm2: pwm@30670000 { 737 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 738 reg = <0x30670000 0x10000>; 739 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 741 <&clk IMX8MN_CLK_PWM2_ROOT>; 742 clock-names = "ipg", "per"; 743 #pwm-cells = <3>; 744 status = "disabled"; 745 }; 746 747 pwm3: pwm@30680000 { 748 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 749 reg = <0x30680000 0x10000>; 750 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 752 <&clk IMX8MN_CLK_PWM3_ROOT>; 753 clock-names = "ipg", "per"; 754 #pwm-cells = <3>; 755 status = "disabled"; 756 }; 757 758 pwm4: pwm@30690000 { 759 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 760 reg = <0x30690000 0x10000>; 761 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 763 <&clk IMX8MN_CLK_PWM4_ROOT>; 764 clock-names = "ipg", "per"; 765 #pwm-cells = <3>; 766 status = "disabled"; 767 }; 768 769 system_counter: timer@306a0000 { 770 compatible = "nxp,sysctr-timer"; 771 reg = <0x306a0000 0x20000>; 772 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&osc_24m>; 774 clock-names = "per"; 775 }; 776 }; 777 778 aips3: bus@30800000 { 779 compatible = "fsl,aips-bus", "simple-bus"; 780 reg = <0x30800000 0x400000>; 781 #address-cells = <1>; 782 #size-cells = <1>; 783 ranges; 784 785 spba1: spba-bus@30800000 { 786 compatible = "fsl,spba-bus", "simple-bus"; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 reg = <0x30800000 0x100000>; 790 ranges; 791 792 ecspi1: spi@30820000 { 793 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 reg = <0x30820000 0x10000>; 797 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 799 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 800 clock-names = "ipg", "per"; 801 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 802 dma-names = "rx", "tx"; 803 status = "disabled"; 804 }; 805 806 ecspi2: spi@30830000 { 807 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 reg = <0x30830000 0x10000>; 811 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 813 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 814 clock-names = "ipg", "per"; 815 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 816 dma-names = "rx", "tx"; 817 status = "disabled"; 818 }; 819 820 ecspi3: spi@30840000 { 821 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 reg = <0x30840000 0x10000>; 825 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 827 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 828 clock-names = "ipg", "per"; 829 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 830 dma-names = "rx", "tx"; 831 status = "disabled"; 832 }; 833 834 uart1: serial@30860000 { 835 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 836 reg = <0x30860000 0x10000>; 837 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 839 <&clk IMX8MN_CLK_UART1_ROOT>; 840 clock-names = "ipg", "per"; 841 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 842 dma-names = "rx", "tx"; 843 status = "disabled"; 844 }; 845 846 uart3: serial@30880000 { 847 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 848 reg = <0x30880000 0x10000>; 849 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 851 <&clk IMX8MN_CLK_UART3_ROOT>; 852 clock-names = "ipg", "per"; 853 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 854 dma-names = "rx", "tx"; 855 status = "disabled"; 856 }; 857 858 uart2: serial@30890000 { 859 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 860 reg = <0x30890000 0x10000>; 861 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 863 <&clk IMX8MN_CLK_UART2_ROOT>; 864 clock-names = "ipg", "per"; 865 status = "disabled"; 866 }; 867 }; 868 869 crypto: crypto@30900000 { 870 compatible = "fsl,sec-v4.0"; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 reg = <0x30900000 0x40000>; 874 ranges = <0 0x30900000 0x40000>; 875 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clk IMX8MN_CLK_AHB>, 877 <&clk IMX8MN_CLK_IPG_ROOT>; 878 clock-names = "aclk", "ipg"; 879 880 sec_jr0: jr@1000 { 881 compatible = "fsl,sec-v4.0-job-ring"; 882 reg = <0x1000 0x1000>; 883 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 884 status = "disabled"; 885 }; 886 887 sec_jr1: jr@2000 { 888 compatible = "fsl,sec-v4.0-job-ring"; 889 reg = <0x2000 0x1000>; 890 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 891 }; 892 893 sec_jr2: jr@3000 { 894 compatible = "fsl,sec-v4.0-job-ring"; 895 reg = <0x3000 0x1000>; 896 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 897 }; 898 }; 899 900 i2c1: i2c@30a20000 { 901 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 reg = <0x30a20000 0x10000>; 905 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 907 status = "disabled"; 908 }; 909 910 i2c2: i2c@30a30000 { 911 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 reg = <0x30a30000 0x10000>; 915 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 917 status = "disabled"; 918 }; 919 920 i2c3: i2c@30a40000 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 924 reg = <0x30a40000 0x10000>; 925 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 927 status = "disabled"; 928 }; 929 930 i2c4: i2c@30a50000 { 931 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 reg = <0x30a50000 0x10000>; 935 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 937 status = "disabled"; 938 }; 939 940 uart4: serial@30a60000 { 941 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 942 reg = <0x30a60000 0x10000>; 943 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 945 <&clk IMX8MN_CLK_UART4_ROOT>; 946 clock-names = "ipg", "per"; 947 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 948 dma-names = "rx", "tx"; 949 status = "disabled"; 950 }; 951 952 mu: mailbox@30aa0000 { 953 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 954 reg = <0x30aa0000 0x10000>; 955 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 957 #mbox-cells = <2>; 958 }; 959 960 usdhc1: mmc@30b40000 { 961 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 962 reg = <0x30b40000 0x10000>; 963 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 965 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 966 <&clk IMX8MN_CLK_USDHC1_ROOT>; 967 clock-names = "ipg", "ahb", "per"; 968 fsl,tuning-start-tap = <20>; 969 fsl,tuning-step = <2>; 970 bus-width = <4>; 971 status = "disabled"; 972 }; 973 974 usdhc2: mmc@30b50000 { 975 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 976 reg = <0x30b50000 0x10000>; 977 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 979 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 980 <&clk IMX8MN_CLK_USDHC2_ROOT>; 981 clock-names = "ipg", "ahb", "per"; 982 fsl,tuning-start-tap = <20>; 983 fsl,tuning-step = <2>; 984 bus-width = <4>; 985 status = "disabled"; 986 }; 987 988 usdhc3: mmc@30b60000 { 989 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 990 reg = <0x30b60000 0x10000>; 991 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 993 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 994 <&clk IMX8MN_CLK_USDHC3_ROOT>; 995 clock-names = "ipg", "ahb", "per"; 996 fsl,tuning-start-tap = <20>; 997 fsl,tuning-step = <2>; 998 bus-width = <4>; 999 status = "disabled"; 1000 }; 1001 1002 flexspi: spi@30bb0000 { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 compatible = "nxp,imx8mm-fspi"; 1006 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1007 reg-names = "fspi_base", "fspi_mmap"; 1008 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 1010 <&clk IMX8MN_CLK_QSPI_ROOT>; 1011 clock-names = "fspi_en", "fspi"; 1012 status = "disabled"; 1013 }; 1014 1015 sdma1: dma-controller@30bd0000 { 1016 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 1017 reg = <0x30bd0000 0x10000>; 1018 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 1020 <&clk IMX8MN_CLK_AHB>; 1021 clock-names = "ipg", "ahb"; 1022 #dma-cells = <3>; 1023 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1024 }; 1025 1026 fec1: ethernet@30be0000 { 1027 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1028 reg = <0x30be0000 0x10000>; 1029 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 1034 <&clk IMX8MN_CLK_ENET1_ROOT>, 1035 <&clk IMX8MN_CLK_ENET_TIMER>, 1036 <&clk IMX8MN_CLK_ENET_REF>, 1037 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1038 clock-names = "ipg", "ahb", "ptp", 1039 "enet_clk_ref", "enet_out"; 1040 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 1041 <&clk IMX8MN_CLK_ENET_TIMER>, 1042 <&clk IMX8MN_CLK_ENET_REF>, 1043 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1044 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1045 <&clk IMX8MN_SYS_PLL2_100M>, 1046 <&clk IMX8MN_SYS_PLL2_125M>, 1047 <&clk IMX8MN_SYS_PLL2_50M>; 1048 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1049 fsl,num-tx-queues = <3>; 1050 fsl,num-rx-queues = <3>; 1051 nvmem-cells = <&fec_mac_address>; 1052 nvmem-cell-names = "mac-address"; 1053 fsl,stop-mode = <&gpr 0x10 3>; 1054 status = "disabled"; 1055 }; 1056 1057 }; 1058 1059 aips4: bus@32c00000 { 1060 compatible = "fsl,aips-bus", "simple-bus"; 1061 reg = <0x32c00000 0x400000>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges; 1065 1066 lcdif: lcdif@32e00000 { 1067 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; 1068 reg = <0x32e00000 0x10000>; 1069 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1070 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1071 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1072 clock-names = "pix", "axi", "disp_axi"; 1073 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; 1075 status = "disabled"; 1076 1077 port { 1078 lcdif_to_dsim: endpoint { 1079 remote-endpoint = <&dsim_from_lcdif>; 1080 }; 1081 }; 1082 }; 1083 1084 mipi_dsi: dsi@32e10000 { 1085 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 1086 reg = <0x32e10000 0x400>; 1087 clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1088 <&clk IMX8MN_CLK_DSI_PHY_REF>; 1089 clock-names = "bus_clk", "sclk_mipi"; 1090 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; 1092 status = "disabled"; 1093 1094 ports { 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 1098 port@0 { 1099 reg = <0>; 1100 1101 dsim_from_lcdif: endpoint { 1102 remote-endpoint = <&lcdif_to_dsim>; 1103 }; 1104 }; 1105 }; 1106 }; 1107 1108 isi: isi@32e20000 { 1109 compatible = "fsl,imx8mn-isi"; 1110 reg = <0x32e20000 0x8000>; 1111 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1113 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 1114 clock-names = "axi", "apb"; 1115 fsl,blk-ctrl = <&disp_blk_ctrl>; 1116 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; 1117 status = "disabled"; 1118 1119 ports { 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 1123 port@0 { 1124 reg = <0>; 1125 isi_in: endpoint { 1126 remote-endpoint = <&mipi_csi_out>; 1127 }; 1128 }; 1129 }; 1130 }; 1131 1132 disp_blk_ctrl: blk-ctrl@32e28000 { 1133 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 1134 reg = <0x32e28000 0x100>; 1135 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1136 <&pgc_dispmix>, <&pgc_mipi>, 1137 <&pgc_mipi>; 1138 power-domain-names = "bus", "isi", 1139 "lcdif", "mipi-dsi", 1140 "mipi-csi"; 1141 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 1142 <&clk IMX8MN_CLK_DISP_APB>, 1143 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1144 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1145 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1146 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1147 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1148 <&clk IMX8MN_CLK_DSI_CORE>, 1149 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1150 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1151 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 1152 clock-names = "disp_axi", "disp_apb", 1153 "disp_axi_root", "disp_apb_root", 1154 "lcdif-axi", "lcdif-apb", "lcdif-pix", 1155 "dsi-pclk", "dsi-ref", 1156 "csi-aclk", "csi-pclk"; 1157 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1158 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1159 <&clk IMX8MN_CLK_DISP_PIXEL>, 1160 <&clk IMX8MN_CLK_DISP_AXI>, 1161 <&clk IMX8MN_CLK_DISP_APB>; 1162 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1163 <&clk IMX8MN_CLK_24M>, 1164 <&clk IMX8MN_VIDEO_PLL1_OUT>, 1165 <&clk IMX8MN_SYS_PLL2_1000M>, 1166 <&clk IMX8MN_SYS_PLL1_800M>; 1167 assigned-clock-rates = <266000000>, 1168 <24000000>, 1169 <594000000>, 1170 <500000000>, 1171 <200000000>; 1172 #power-domain-cells = <1>; 1173 }; 1174 1175 mipi_csi: mipi-csi@32e30000 { 1176 compatible = "fsl,imx8mm-mipi-csi2"; 1177 reg = <0x32e30000 0x1000>; 1178 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1179 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; 1180 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; 1181 assigned-clock-rates = <333000000>; 1182 clock-frequency = <333000000>; 1183 clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1184 <&clk IMX8MN_CLK_CAMERA_PIXEL>, 1185 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1186 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1187 clock-names = "pclk", "wrap", "phy", "axi"; 1188 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; 1189 status = "disabled"; 1190 1191 ports { 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 1195 port@0 { 1196 reg = <0>; 1197 }; 1198 1199 port@1 { 1200 reg = <1>; 1201 1202 mipi_csi_out: endpoint { 1203 remote-endpoint = <&isi_in>; 1204 }; 1205 }; 1206 }; 1207 }; 1208 1209 usbotg1: usb@32e40000 { 1210 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1211 reg = <0x32e40000 0x200>; 1212 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1214 clock-names = "usb1_ctrl_root_clk"; 1215 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1216 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1217 phys = <&usbphynop1>; 1218 fsl,usbmisc = <&usbmisc1 0>; 1219 power-domains = <&pgc_hsiomix>; 1220 status = "disabled"; 1221 }; 1222 1223 usbmisc1: usbmisc@32e40200 { 1224 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", 1225 "fsl,imx6q-usbmisc"; 1226 #index-cells = <1>; 1227 reg = <0x32e40200 0x200>; 1228 }; 1229 }; 1230 1231 dma_apbh: dma-controller@33000000 { 1232 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1233 reg = <0x33000000 0x2000>; 1234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1238 #dma-cells = <1>; 1239 dma-channels = <4>; 1240 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1241 }; 1242 1243 gpmi: nand-controller@33002000 { 1244 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1248 reg-names = "gpmi-nand", "bch"; 1249 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1250 interrupt-names = "bch"; 1251 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1252 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1253 clock-names = "gpmi_io", "gpmi_bch_apb"; 1254 dmas = <&dma_apbh 0>; 1255 dma-names = "rx-tx"; 1256 status = "disabled"; 1257 }; 1258 1259 gpu: gpu@38000000 { 1260 compatible = "vivante,gc"; 1261 reg = <0x38000000 0x8000>; 1262 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&clk IMX8MN_CLK_GPU_AHB>, 1264 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 1265 <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 1266 <&clk IMX8MN_CLK_GPU_SHADER>; 1267 clock-names = "reg", "bus", "core", "shader"; 1268 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, 1269 <&clk IMX8MN_CLK_GPU_SHADER>, 1270 <&clk IMX8MN_CLK_GPU_AXI>, 1271 <&clk IMX8MN_CLK_GPU_AHB>, 1272 <&clk IMX8MN_GPU_PLL>; 1273 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, 1274 <&clk IMX8MN_GPU_PLL_OUT>, 1275 <&clk IMX8MN_SYS_PLL1_800M>, 1276 <&clk IMX8MN_SYS_PLL1_800M>; 1277 assigned-clock-rates = <400000000>, 1278 <400000000>, 1279 <800000000>, 1280 <400000000>, 1281 <1200000000>; 1282 power-domains = <&pgc_gpumix>; 1283 }; 1284 1285 gic: interrupt-controller@38800000 { 1286 compatible = "arm,gic-v3"; 1287 reg = <0x38800000 0x10000>, 1288 <0x38880000 0xc0000>; 1289 #interrupt-cells = <3>; 1290 interrupt-controller; 1291 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1292 }; 1293 1294 ddrc: memory-controller@3d400000 { 1295 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1296 reg = <0x3d400000 0x400000>; 1297 clock-names = "core", "pll", "alt", "apb"; 1298 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1299 <&clk IMX8MN_DRAM_PLL>, 1300 <&clk IMX8MN_CLK_DRAM_ALT>, 1301 <&clk IMX8MN_CLK_DRAM_APB>; 1302 }; 1303 1304 ddr-pmu@3d800000 { 1305 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1306 reg = <0x3d800000 0x400000>; 1307 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1308 }; 1309 }; 1310 1311 usbphynop1: usbphynop1 { 1312 #phy-cells = <0>; 1313 compatible = "usb-nop-xceiv"; 1314 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1315 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1316 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1317 clock-names = "main_clk"; 1318 power-domains = <&pgc_otg1>; 1319 }; 1320}; 1321