1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/power/imx8mn-power.h>
8#include <dt-bindings/reset/imx8mq-reset.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/thermal/thermal.h>
13
14#include "imx8mn-pinfunc.h"
15
16/ {
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		ethernet0 = &fec1;
23		gpio0 = &gpio1;
24		gpio1 = &gpio2;
25		gpio2 = &gpio3;
26		gpio3 = &gpio4;
27		gpio4 = &gpio5;
28		i2c0 = &i2c1;
29		i2c1 = &i2c2;
30		i2c2 = &i2c3;
31		i2c3 = &i2c4;
32		mmc0 = &usdhc1;
33		mmc1 = &usdhc2;
34		mmc2 = &usdhc3;
35		serial0 = &uart1;
36		serial1 = &uart2;
37		serial2 = &uart3;
38		serial3 = &uart4;
39		spi0 = &ecspi1;
40		spi1 = &ecspi2;
41		spi2 = &ecspi3;
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		idle-states {
49			entry-method = "psci";
50
51			cpu_pd_wait: cpu-pd-wait {
52				compatible = "arm,idle-state";
53				arm,psci-suspend-param = <0x0010033>;
54				local-timer-stop;
55				entry-latency-us = <1000>;
56				exit-latency-us = <700>;
57				min-residency-us = <2700>;
58			};
59		};
60
61		A53_0: cpu@0 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a53";
64			reg = <0x0>;
65			clock-latency = <61036>;
66			clocks = <&clk IMX8MN_CLK_ARM>;
67			enable-method = "psci";
68			i-cache-size = <0x8000>;
69			i-cache-line-size = <64>;
70			i-cache-sets = <256>;
71			d-cache-size = <0x8000>;
72			d-cache-line-size = <64>;
73			d-cache-sets = <128>;
74			next-level-cache = <&A53_L2>;
75			operating-points-v2 = <&a53_opp_table>;
76			nvmem-cells = <&cpu_speed_grade>;
77			nvmem-cell-names = "speed_grade";
78			cpu-idle-states = <&cpu_pd_wait>;
79			#cooling-cells = <2>;
80		};
81
82		A53_1: cpu@1 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			reg = <0x1>;
86			clock-latency = <61036>;
87			clocks = <&clk IMX8MN_CLK_ARM>;
88			enable-method = "psci";
89			i-cache-size = <0x8000>;
90			i-cache-line-size = <64>;
91			i-cache-sets = <256>;
92			d-cache-size = <0x8000>;
93			d-cache-line-size = <64>;
94			d-cache-sets = <128>;
95			next-level-cache = <&A53_L2>;
96			operating-points-v2 = <&a53_opp_table>;
97			cpu-idle-states = <&cpu_pd_wait>;
98			#cooling-cells = <2>;
99		};
100
101		A53_2: cpu@2 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a53";
104			reg = <0x2>;
105			clock-latency = <61036>;
106			clocks = <&clk IMX8MN_CLK_ARM>;
107			enable-method = "psci";
108			i-cache-size = <0x8000>;
109			i-cache-line-size = <64>;
110			i-cache-sets = <256>;
111			d-cache-size = <0x8000>;
112			d-cache-line-size = <64>;
113			d-cache-sets = <128>;
114			next-level-cache = <&A53_L2>;
115			operating-points-v2 = <&a53_opp_table>;
116			cpu-idle-states = <&cpu_pd_wait>;
117			#cooling-cells = <2>;
118		};
119
120		A53_3: cpu@3 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a53";
123			reg = <0x3>;
124			clock-latency = <61036>;
125			clocks = <&clk IMX8MN_CLK_ARM>;
126			enable-method = "psci";
127			i-cache-size = <0x8000>;
128			i-cache-line-size = <64>;
129			i-cache-sets = <256>;
130			d-cache-size = <0x8000>;
131			d-cache-line-size = <64>;
132			d-cache-sets = <128>;
133			next-level-cache = <&A53_L2>;
134			operating-points-v2 = <&a53_opp_table>;
135			cpu-idle-states = <&cpu_pd_wait>;
136			#cooling-cells = <2>;
137		};
138
139		A53_L2: l2-cache0 {
140			compatible = "cache";
141			cache-level = <2>;
142			cache-unified;
143			cache-size = <0x80000>;
144			cache-line-size = <64>;
145			cache-sets = <512>;
146		};
147	};
148
149	a53_opp_table: opp-table {
150		compatible = "operating-points-v2";
151		opp-shared;
152
153		opp-1200000000 {
154			opp-hz = /bits/ 64 <1200000000>;
155			opp-microvolt = <850000>;
156			opp-supported-hw = <0xb00>, <0x7>;
157			clock-latency-ns = <150000>;
158			opp-suspend;
159		};
160
161		opp-1400000000 {
162			opp-hz = /bits/ 64 <1400000000>;
163			opp-microvolt = <950000>;
164			opp-supported-hw = <0x300>, <0x7>;
165			clock-latency-ns = <150000>;
166			opp-suspend;
167		};
168
169		opp-1500000000 {
170			opp-hz = /bits/ 64 <1500000000>;
171			opp-microvolt = <1000000>;
172			opp-supported-hw = <0x100>, <0x3>;
173			clock-latency-ns = <150000>;
174			opp-suspend;
175		};
176	};
177
178	osc_32k: clock-osc-32k {
179		compatible = "fixed-clock";
180		#clock-cells = <0>;
181		clock-frequency = <32768>;
182		clock-output-names = "osc_32k";
183	};
184
185	osc_24m: clock-osc-24m {
186		compatible = "fixed-clock";
187		#clock-cells = <0>;
188		clock-frequency = <24000000>;
189		clock-output-names = "osc_24m";
190	};
191
192	clk_ext1: clock-ext1 {
193		compatible = "fixed-clock";
194		#clock-cells = <0>;
195		clock-frequency = <133000000>;
196		clock-output-names = "clk_ext1";
197	};
198
199	clk_ext2: clock-ext2 {
200		compatible = "fixed-clock";
201		#clock-cells = <0>;
202		clock-frequency = <133000000>;
203		clock-output-names = "clk_ext2";
204	};
205
206	clk_ext3: clock-ext3 {
207		compatible = "fixed-clock";
208		#clock-cells = <0>;
209		clock-frequency = <133000000>;
210		clock-output-names = "clk_ext3";
211	};
212
213	clk_ext4: clock-ext4 {
214		compatible = "fixed-clock";
215		#clock-cells = <0>;
216		clock-frequency = <133000000>;
217		clock-output-names = "clk_ext4";
218	};
219
220	pmu {
221		compatible = "arm,cortex-a53-pmu";
222		interrupts = <GIC_PPI 7
223			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
224	};
225
226	psci {
227		compatible = "arm,psci-1.0";
228		method = "smc";
229	};
230
231	thermal-zones {
232		cpu-thermal {
233			polling-delay-passive = <250>;
234			polling-delay = <2000>;
235			thermal-sensors = <&tmu>;
236			trips {
237				cpu_alert0: trip0 {
238					temperature = <85000>;
239					hysteresis = <2000>;
240					type = "passive";
241				};
242
243				cpu_crit0: trip1 {
244					temperature = <95000>;
245					hysteresis = <2000>;
246					type = "critical";
247				};
248			};
249
250			cooling-maps {
251				map0 {
252					trip = <&cpu_alert0>;
253					cooling-device =
254						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
257						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
258				};
259			};
260		};
261	};
262
263	timer {
264		compatible = "arm,armv8-timer";
265		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
266			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
267			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
268			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
269		clock-frequency = <8000000>;
270		arm,no-tick-in-suspend;
271	};
272
273	soc: soc@0 {
274		compatible = "fsl,imx8mn-soc", "simple-bus";
275		#address-cells = <1>;
276		#size-cells = <1>;
277		ranges = <0x0 0x0 0x0 0x3e000000>;
278		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
279		nvmem-cells = <&imx8mn_uid>;
280		nvmem-cell-names = "soc_unique_id";
281
282		aips1: bus@30000000 {
283			compatible = "fsl,aips-bus", "simple-bus";
284			reg = <0x30000000 0x400000>;
285			#address-cells = <1>;
286			#size-cells = <1>;
287			ranges;
288
289			spba2: spba-bus@30000000 {
290				compatible = "fsl,spba-bus", "simple-bus";
291				#address-cells = <1>;
292				#size-cells = <1>;
293				reg = <0x30000000 0x100000>;
294				ranges;
295
296				sai2: sai@30020000 {
297					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
298					reg = <0x30020000 0x10000>;
299					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
300					clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
301						<&clk IMX8MN_CLK_DUMMY>,
302						<&clk IMX8MN_CLK_SAI2_ROOT>,
303						<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
304					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
305					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
306					dma-names = "rx", "tx";
307					status = "disabled";
308				};
309
310				sai3: sai@30030000 {
311					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
312					reg = <0x30030000 0x10000>;
313					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
314					clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
315						 <&clk IMX8MN_CLK_DUMMY>,
316						 <&clk IMX8MN_CLK_SAI3_ROOT>,
317						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
318					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
319					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
320					dma-names = "rx", "tx";
321					status = "disabled";
322				};
323
324				sai5: sai@30050000 {
325					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
326					reg = <0x30050000 0x10000>;
327					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
328					clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
329						 <&clk IMX8MN_CLK_DUMMY>,
330						 <&clk IMX8MN_CLK_SAI5_ROOT>,
331						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
332					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
333					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
334					dma-names = "rx", "tx";
335					fsl,shared-interrupt;
336					fsl,dataline = <0 0xf 0xf>;
337					status = "disabled";
338				};
339
340				sai6: sai@30060000 {
341					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
342					reg = <0x30060000  0x10000>;
343					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
344					clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
345						 <&clk IMX8MN_CLK_DUMMY>,
346						 <&clk IMX8MN_CLK_SAI6_ROOT>,
347						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
348					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
349					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
350					dma-names = "rx", "tx";
351					status = "disabled";
352				};
353
354				micfil: audio-controller@30080000 {
355					compatible = "fsl,imx8mm-micfil";
356					reg = <0x30080000 0x10000>;
357					interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
358						     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
359						     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
360						     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
361					clocks = <&clk IMX8MN_CLK_PDM_IPG>,
362						 <&clk IMX8MN_CLK_PDM_ROOT>,
363						 <&clk IMX8MN_AUDIO_PLL1_OUT>,
364						 <&clk IMX8MN_AUDIO_PLL2_OUT>,
365						 <&clk IMX8MN_CLK_EXT3>;
366					clock-names = "ipg_clk", "ipg_clk_app",
367						      "pll8k", "pll11k", "clkext3";
368					dmas = <&sdma2 24 25 0x80000000>;
369					dma-names = "rx";
370					status = "disabled";
371				};
372
373				spdif1: spdif@30090000 {
374					compatible = "fsl,imx35-spdif";
375					reg = <0x30090000 0x10000>;
376					interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
377					clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
378						 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
379						 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
380						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
381						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
382						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
383						 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
384						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
385						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
386						 <&clk IMX8MN_CLK_DUMMY>; /* spba */
387					clock-names = "core", "rxtx0",
388						      "rxtx1", "rxtx2",
389						      "rxtx3", "rxtx4",
390						      "rxtx5", "rxtx6",
391						      "rxtx7", "spba";
392					dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
393					dma-names = "rx", "tx";
394					status = "disabled";
395				};
396
397				sai7: sai@300b0000 {
398					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
399					reg = <0x300b0000 0x10000>;
400					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
401					clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
402						 <&clk IMX8MN_CLK_DUMMY>,
403						 <&clk IMX8MN_CLK_SAI7_ROOT>,
404						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
405					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
406					dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
407					dma-names = "rx", "tx";
408					status = "disabled";
409				};
410
411				easrc: easrc@300c0000 {
412					compatible = "fsl,imx8mn-easrc";
413					reg = <0x300c0000 0x10000>;
414					interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
415					clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
416					clock-names = "mem";
417					dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
418					       <&sdma2 18 23 0> , <&sdma2 19 23 0>,
419					       <&sdma2 20 23 0> , <&sdma2 21 23 0>,
420					       <&sdma2 22 23 0> , <&sdma2 23 23 0>;
421					dma-names = "ctx0_rx", "ctx0_tx",
422						    "ctx1_rx", "ctx1_tx",
423						    "ctx2_rx", "ctx2_tx",
424						    "ctx3_rx", "ctx3_tx";
425					firmware-name = "imx/easrc/easrc-imx8mn.bin";
426					fsl,asrc-rate = <8000>;
427					fsl,asrc-format = <2>;
428					status = "disabled";
429				};
430			};
431
432			gpio1: gpio@30200000 {
433				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
434				reg = <0x30200000 0x10000>;
435				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
436					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
437				clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
438				gpio-controller;
439				#gpio-cells = <2>;
440				interrupt-controller;
441				#interrupt-cells = <2>;
442				gpio-ranges = <&iomuxc 0 10 30>;
443			};
444
445			gpio2: gpio@30210000 {
446				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
447				reg = <0x30210000 0x10000>;
448				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
449					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
450				clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
451				gpio-controller;
452				#gpio-cells = <2>;
453				interrupt-controller;
454				#interrupt-cells = <2>;
455				gpio-ranges = <&iomuxc 0 40 21>;
456			};
457
458			gpio3: gpio@30220000 {
459				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
460				reg = <0x30220000 0x10000>;
461				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
462					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
463				clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
464				gpio-controller;
465				#gpio-cells = <2>;
466				interrupt-controller;
467				#interrupt-cells = <2>;
468				gpio-ranges = <&iomuxc 0 61 26>;
469			};
470
471			gpio4: gpio@30230000 {
472				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
473				reg = <0x30230000 0x10000>;
474				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
475					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
476				clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
477				gpio-controller;
478				#gpio-cells = <2>;
479				interrupt-controller;
480				#interrupt-cells = <2>;
481				gpio-ranges = <&iomuxc 21 108 11>;
482			};
483
484			gpio5: gpio@30240000 {
485				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
486				reg = <0x30240000 0x10000>;
487				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
488					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
489				clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
490				gpio-controller;
491				#gpio-cells = <2>;
492				interrupt-controller;
493				#interrupt-cells = <2>;
494				gpio-ranges = <&iomuxc 0 119 30>;
495			};
496
497			tmu: tmu@30260000 {
498				compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
499				reg = <0x30260000 0x10000>;
500				clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
501				nvmem-cells = <&tmu_calib>;
502				nvmem-cell-names = "calib";
503				#thermal-sensor-cells = <0>;
504			};
505
506			wdog1: watchdog@30280000 {
507				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
508				reg = <0x30280000 0x10000>;
509				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
510				clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
511				status = "disabled";
512			};
513
514			wdog2: watchdog@30290000 {
515				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
516				reg = <0x30290000 0x10000>;
517				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
518				clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
519				status = "disabled";
520			};
521
522			wdog3: watchdog@302a0000 {
523				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
524				reg = <0x302a0000 0x10000>;
525				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
526				clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
527				status = "disabled";
528			};
529
530			sdma3: dma-controller@302b0000 {
531				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
532				reg = <0x302b0000 0x10000>;
533				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
534				clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
535				 <&clk IMX8MN_CLK_SDMA3_ROOT>;
536				clock-names = "ipg", "ahb";
537				#dma-cells = <3>;
538				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
539			};
540
541			sdma2: dma-controller@302c0000 {
542				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
543				reg = <0x302c0000 0x10000>;
544				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
545				clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
546					 <&clk IMX8MN_CLK_SDMA2_ROOT>;
547				clock-names = "ipg", "ahb";
548				#dma-cells = <3>;
549				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
550			};
551
552			iomuxc: pinctrl@30330000 {
553				compatible = "fsl,imx8mn-iomuxc";
554				reg = <0x30330000 0x10000>;
555			};
556
557			gpr: syscon@30340000 {
558				compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
559				reg = <0x30340000 0x10000>;
560			};
561
562			ocotp: efuse@30350000 {
563				compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
564				reg = <0x30350000 0x10000>;
565				clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
566				#address-cells = <1>;
567				#size-cells = <1>;
568
569				/*
570				 * The register address below maps to the MX8M
571				 * Fusemap Description Table entries this way.
572				 * Assuming
573				 *   reg = <ADDR SIZE>;
574				 * then
575				 *   Fuse Address = (ADDR * 4) + 0x400
576				 * Note that if SIZE is greater than 4, then
577				 * each subsequent fuse is located at offset
578				 * +0x10 in Fusemap Description Table (e.g.
579				 * reg = <0x4 0x8> describes fuses 0x410 and
580				 * 0x420).
581				 */
582				imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
583					reg = <0x4 0x8>;
584				};
585
586				cpu_speed_grade: speed-grade@10 { /* 0x440 */
587					reg = <0x10 4>;
588				};
589
590				tmu_calib: calib@3c { /* 0x4f0 */
591					reg = <0x3c 4>;
592				};
593
594				fec_mac_address: mac-address@90 { /* 0x640 */
595					reg = <0x90 6>;
596				};
597			};
598
599			anatop: clock-controller@30360000 {
600				compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
601				reg = <0x30360000 0x10000>;
602				#clock-cells = <1>;
603			};
604
605			snvs: snvs@30370000 {
606				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
607				reg = <0x30370000 0x10000>;
608
609				snvs_rtc: snvs-rtc-lp {
610					compatible = "fsl,sec-v4.0-mon-rtc-lp";
611					regmap = <&snvs>;
612					offset = <0x34>;
613					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
614						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
615					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
616					clock-names = "snvs-rtc";
617				};
618
619				snvs_pwrkey: snvs-powerkey {
620					compatible = "fsl,sec-v4.0-pwrkey";
621					regmap = <&snvs>;
622					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
623					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
624					clock-names = "snvs-pwrkey";
625					linux,keycode = <KEY_POWER>;
626					wakeup-source;
627					status = "disabled";
628				};
629			};
630
631			clk: clock-controller@30380000 {
632				compatible = "fsl,imx8mn-ccm";
633				reg = <0x30380000 0x10000>;
634				#clock-cells = <1>;
635				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
636					 <&clk_ext3>, <&clk_ext4>;
637				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
638					      "clk_ext3", "clk_ext4";
639				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
640						<&clk IMX8MN_CLK_A53_CORE>,
641						<&clk IMX8MN_CLK_NOC>,
642						<&clk IMX8MN_CLK_AUDIO_AHB>,
643						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
644						<&clk IMX8MN_SYS_PLL3>,
645						<&clk IMX8MN_AUDIO_PLL1>,
646						<&clk IMX8MN_AUDIO_PLL2>;
647				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
648							 <&clk IMX8MN_ARM_PLL_OUT>,
649							 <&clk IMX8MN_SYS_PLL3_OUT>,
650							 <&clk IMX8MN_SYS_PLL1_800M>;
651				assigned-clock-rates = <0>, <0>, <0>,
652							<400000000>,
653							<400000000>,
654							<600000000>,
655							<393216000>,
656							<361267200>;
657			};
658
659			src: reset-controller@30390000 {
660				compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
661				reg = <0x30390000 0x10000>;
662				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
663				#reset-cells = <1>;
664			};
665
666			gpc: gpc@303a0000 {
667				compatible = "fsl,imx8mn-gpc";
668				reg = <0x303a0000 0x10000>;
669				interrupt-parent = <&gic>;
670				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
671
672				pgc {
673					#address-cells = <1>;
674					#size-cells = <0>;
675
676					pgc_hsiomix: power-domain@0 {
677						#power-domain-cells = <0>;
678						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
679						clocks = <&clk IMX8MN_CLK_USB_BUS>;
680					};
681
682					pgc_otg1: power-domain@1 {
683						#power-domain-cells = <0>;
684						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
685					};
686
687					pgc_gpumix: power-domain@2 {
688						#power-domain-cells = <0>;
689						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
690						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
691							 <&clk IMX8MN_CLK_GPU_SHADER>,
692							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
693							 <&clk IMX8MN_CLK_GPU_AHB>;
694					};
695
696					pgc_dispmix: power-domain@3 {
697						#power-domain-cells = <0>;
698						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
699						clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
700							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
701					};
702
703					pgc_mipi: power-domain@4 {
704						#power-domain-cells = <0>;
705						reg = <IMX8MN_POWER_DOMAIN_MIPI>;
706						power-domains = <&pgc_dispmix>;
707					};
708				};
709			};
710		};
711
712		aips2: bus@30400000 {
713			compatible = "fsl,aips-bus", "simple-bus";
714			reg = <0x30400000 0x400000>;
715			#address-cells = <1>;
716			#size-cells = <1>;
717			ranges;
718
719			pwm1: pwm@30660000 {
720				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
721				reg = <0x30660000 0x10000>;
722				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
723				clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
724					<&clk IMX8MN_CLK_PWM1_ROOT>;
725				clock-names = "ipg", "per";
726				#pwm-cells = <3>;
727				status = "disabled";
728			};
729
730			pwm2: pwm@30670000 {
731				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
732				reg = <0x30670000 0x10000>;
733				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
734				clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
735					 <&clk IMX8MN_CLK_PWM2_ROOT>;
736				clock-names = "ipg", "per";
737				#pwm-cells = <3>;
738				status = "disabled";
739			};
740
741			pwm3: pwm@30680000 {
742				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
743				reg = <0x30680000 0x10000>;
744				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
745				clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
746					 <&clk IMX8MN_CLK_PWM3_ROOT>;
747				clock-names = "ipg", "per";
748				#pwm-cells = <3>;
749				status = "disabled";
750			};
751
752			pwm4: pwm@30690000 {
753				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
754				reg = <0x30690000 0x10000>;
755				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
756				clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
757					 <&clk IMX8MN_CLK_PWM4_ROOT>;
758				clock-names = "ipg", "per";
759				#pwm-cells = <3>;
760				status = "disabled";
761			};
762
763			system_counter: timer@306a0000 {
764				compatible = "nxp,sysctr-timer";
765				reg = <0x306a0000 0x20000>;
766				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
767				clocks = <&osc_24m>;
768				clock-names = "per";
769			};
770		};
771
772		aips3: bus@30800000 {
773			compatible = "fsl,aips-bus", "simple-bus";
774			reg = <0x30800000 0x400000>;
775			#address-cells = <1>;
776			#size-cells = <1>;
777			ranges;
778
779			spba1: spba-bus@30800000 {
780				compatible = "fsl,spba-bus", "simple-bus";
781				#address-cells = <1>;
782				#size-cells = <1>;
783				reg = <0x30800000 0x100000>;
784				ranges;
785
786				ecspi1: spi@30820000 {
787					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
788					#address-cells = <1>;
789					#size-cells = <0>;
790					reg = <0x30820000 0x10000>;
791					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
792					clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
793						 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
794					clock-names = "ipg", "per";
795					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
796					dma-names = "rx", "tx";
797					status = "disabled";
798				};
799
800				ecspi2: spi@30830000 {
801					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
802					#address-cells = <1>;
803					#size-cells = <0>;
804					reg = <0x30830000 0x10000>;
805					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
806					clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
807						 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
808					clock-names = "ipg", "per";
809					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
810					dma-names = "rx", "tx";
811					status = "disabled";
812				};
813
814				ecspi3: spi@30840000 {
815					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
816					#address-cells = <1>;
817					#size-cells = <0>;
818					reg = <0x30840000 0x10000>;
819					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
820					clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
821						 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
822					clock-names = "ipg", "per";
823					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
824					dma-names = "rx", "tx";
825					status = "disabled";
826				};
827
828				uart1: serial@30860000 {
829					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
830					reg = <0x30860000 0x10000>;
831					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
832					clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
833						 <&clk IMX8MN_CLK_UART1_ROOT>;
834					clock-names = "ipg", "per";
835					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
836					dma-names = "rx", "tx";
837					status = "disabled";
838				};
839
840				uart3: serial@30880000 {
841					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
842					reg = <0x30880000 0x10000>;
843					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
844					clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
845						 <&clk IMX8MN_CLK_UART3_ROOT>;
846					clock-names = "ipg", "per";
847					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
848					dma-names = "rx", "tx";
849					status = "disabled";
850				};
851
852				uart2: serial@30890000 {
853					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
854					reg = <0x30890000 0x10000>;
855					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
856					clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
857						 <&clk IMX8MN_CLK_UART2_ROOT>;
858					clock-names = "ipg", "per";
859					status = "disabled";
860				};
861			};
862
863			crypto: crypto@30900000 {
864				compatible = "fsl,sec-v4.0";
865				#address-cells = <1>;
866				#size-cells = <1>;
867				reg = <0x30900000 0x40000>;
868				ranges = <0 0x30900000 0x40000>;
869				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
870				clocks = <&clk IMX8MN_CLK_AHB>,
871					 <&clk IMX8MN_CLK_IPG_ROOT>;
872				clock-names = "aclk", "ipg";
873
874				sec_jr0: jr@1000 {
875					 compatible = "fsl,sec-v4.0-job-ring";
876					 reg = <0x1000 0x1000>;
877					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
878					 status = "disabled";
879				};
880
881				sec_jr1: jr@2000 {
882					 compatible = "fsl,sec-v4.0-job-ring";
883					 reg = <0x2000 0x1000>;
884					 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
885				};
886
887				sec_jr2: jr@3000 {
888					 compatible = "fsl,sec-v4.0-job-ring";
889					 reg = <0x3000 0x1000>;
890					 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
891				};
892			};
893
894			i2c1: i2c@30a20000 {
895				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
896				#address-cells = <1>;
897				#size-cells = <0>;
898				reg = <0x30a20000 0x10000>;
899				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
900				clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
901				status = "disabled";
902			};
903
904			i2c2: i2c@30a30000 {
905				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
906				#address-cells = <1>;
907				#size-cells = <0>;
908				reg = <0x30a30000 0x10000>;
909				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
910				clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
911				status = "disabled";
912			};
913
914			i2c3: i2c@30a40000 {
915				#address-cells = <1>;
916				#size-cells = <0>;
917				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
918				reg = <0x30a40000 0x10000>;
919				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
920				clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
921				status = "disabled";
922			};
923
924			i2c4: i2c@30a50000 {
925				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
926				#address-cells = <1>;
927				#size-cells = <0>;
928				reg = <0x30a50000 0x10000>;
929				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
930				clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
931				status = "disabled";
932			};
933
934			uart4: serial@30a60000 {
935				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
936				reg = <0x30a60000 0x10000>;
937				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
938				clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
939					 <&clk IMX8MN_CLK_UART4_ROOT>;
940				clock-names = "ipg", "per";
941				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
942				dma-names = "rx", "tx";
943				status = "disabled";
944			};
945
946			mu: mailbox@30aa0000 {
947				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
948				reg = <0x30aa0000 0x10000>;
949				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
950				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
951				#mbox-cells = <2>;
952			};
953
954			usdhc1: mmc@30b40000 {
955				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
956				reg = <0x30b40000 0x10000>;
957				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
958				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
959					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
960					 <&clk IMX8MN_CLK_USDHC1_ROOT>;
961				clock-names = "ipg", "ahb", "per";
962				fsl,tuning-start-tap = <20>;
963				fsl,tuning-step = <2>;
964				bus-width = <4>;
965				status = "disabled";
966			};
967
968			usdhc2: mmc@30b50000 {
969				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
970				reg = <0x30b50000 0x10000>;
971				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
972				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
973					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
974					 <&clk IMX8MN_CLK_USDHC2_ROOT>;
975				clock-names = "ipg", "ahb", "per";
976				fsl,tuning-start-tap = <20>;
977				fsl,tuning-step = <2>;
978				bus-width = <4>;
979				status = "disabled";
980			};
981
982			usdhc3: mmc@30b60000 {
983				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
984				reg = <0x30b60000 0x10000>;
985				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
986				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
987					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
988					 <&clk IMX8MN_CLK_USDHC3_ROOT>;
989				clock-names = "ipg", "ahb", "per";
990				fsl,tuning-start-tap = <20>;
991				fsl,tuning-step = <2>;
992				bus-width = <4>;
993				status = "disabled";
994			};
995
996			flexspi: spi@30bb0000 {
997				#address-cells = <1>;
998				#size-cells = <0>;
999				compatible = "nxp,imx8mm-fspi";
1000				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1001				reg-names = "fspi_base", "fspi_mmap";
1002				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1003				clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
1004					 <&clk IMX8MN_CLK_QSPI_ROOT>;
1005				clock-names = "fspi_en", "fspi";
1006				status = "disabled";
1007			};
1008
1009			sdma1: dma-controller@30bd0000 {
1010				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
1011				reg = <0x30bd0000 0x10000>;
1012				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1013				clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
1014					 <&clk IMX8MN_CLK_AHB>;
1015				clock-names = "ipg", "ahb";
1016				#dma-cells = <3>;
1017				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1018			};
1019
1020			fec1: ethernet@30be0000 {
1021				compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1022				reg = <0x30be0000 0x10000>;
1023				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1024					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1025					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1026					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1027				clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1028					 <&clk IMX8MN_CLK_ENET1_ROOT>,
1029					 <&clk IMX8MN_CLK_ENET_TIMER>,
1030					 <&clk IMX8MN_CLK_ENET_REF>,
1031					 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1032				clock-names = "ipg", "ahb", "ptp",
1033					      "enet_clk_ref", "enet_out";
1034				assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1035						  <&clk IMX8MN_CLK_ENET_TIMER>,
1036						  <&clk IMX8MN_CLK_ENET_REF>,
1037						  <&clk IMX8MN_CLK_ENET_PHY_REF>;
1038				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1039							 <&clk IMX8MN_SYS_PLL2_100M>,
1040							 <&clk IMX8MN_SYS_PLL2_125M>,
1041							 <&clk IMX8MN_SYS_PLL2_50M>;
1042				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1043				fsl,num-tx-queues = <3>;
1044				fsl,num-rx-queues = <3>;
1045				nvmem-cells = <&fec_mac_address>;
1046				nvmem-cell-names = "mac-address";
1047				fsl,stop-mode = <&gpr 0x10 3>;
1048				status = "disabled";
1049			};
1050
1051		};
1052
1053		aips4: bus@32c00000 {
1054			compatible = "fsl,aips-bus", "simple-bus";
1055			reg = <0x32c00000 0x400000>;
1056			#address-cells = <1>;
1057			#size-cells = <1>;
1058			ranges;
1059
1060			disp_blk_ctrl: blk-ctrl@32e28000 {
1061				compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1062				reg = <0x32e28000 0x100>;
1063				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1064						<&pgc_dispmix>, <&pgc_mipi>,
1065						<&pgc_mipi>;
1066				power-domain-names = "bus", "isi",
1067						     "lcdif", "mipi-dsi",
1068						     "mipi-csi";
1069				clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1070					 <&clk IMX8MN_CLK_DISP_APB>,
1071					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1072					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1073					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1074					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1075					 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1076					 <&clk IMX8MN_CLK_DSI_CORE>,
1077					 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1078					 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1079					 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1080				clock-names = "disp_axi", "disp_apb",
1081					      "disp_axi_root", "disp_apb_root",
1082					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
1083					      "dsi-pclk", "dsi-ref",
1084					      "csi-aclk", "csi-pclk";
1085				#power-domain-cells = <1>;
1086			};
1087
1088			usbotg1: usb@32e40000 {
1089				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1090				reg = <0x32e40000 0x200>;
1091				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1092				clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1093				clock-names = "usb1_ctrl_root_clk";
1094				assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1095				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1096				phys = <&usbphynop1>;
1097				fsl,usbmisc = <&usbmisc1 0>;
1098				power-domains = <&pgc_hsiomix>;
1099				status = "disabled";
1100			};
1101
1102			usbmisc1: usbmisc@32e40200 {
1103				compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1104				#index-cells = <1>;
1105				reg = <0x32e40200 0x200>;
1106			};
1107		};
1108
1109		dma_apbh: dma-controller@33000000 {
1110			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1111			reg = <0x33000000 0x2000>;
1112			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1113				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1114				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1115				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1116			#dma-cells = <1>;
1117			dma-channels = <4>;
1118			clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1119		};
1120
1121		gpmi: nand-controller@33002000 {
1122			compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1123			#address-cells = <1>;
1124			#size-cells = <0>;
1125			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1126			reg-names = "gpmi-nand", "bch";
1127			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1128			interrupt-names = "bch";
1129			clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1130				 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1131			clock-names = "gpmi_io", "gpmi_bch_apb";
1132			dmas = <&dma_apbh 0>;
1133			dma-names = "rx-tx";
1134			status = "disabled";
1135		};
1136
1137		gpu: gpu@38000000 {
1138			compatible = "vivante,gc";
1139			reg = <0x38000000 0x8000>;
1140			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1141			clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1142				<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1143				<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1144				<&clk IMX8MN_CLK_GPU_SHADER>;
1145			clock-names = "reg", "bus", "core", "shader";
1146			assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1147					  <&clk IMX8MN_CLK_GPU_SHADER>,
1148					  <&clk IMX8MN_CLK_GPU_AXI>,
1149					  <&clk IMX8MN_CLK_GPU_AHB>,
1150					  <&clk IMX8MN_GPU_PLL>;
1151			assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1152						  <&clk IMX8MN_GPU_PLL_OUT>,
1153						  <&clk IMX8MN_SYS_PLL1_800M>,
1154						  <&clk IMX8MN_SYS_PLL1_800M>;
1155			assigned-clock-rates = <400000000>,
1156					       <400000000>,
1157					       <800000000>,
1158					       <400000000>,
1159					       <1200000000>;
1160			power-domains = <&pgc_gpumix>;
1161		};
1162
1163		gic: interrupt-controller@38800000 {
1164			compatible = "arm,gic-v3";
1165			reg = <0x38800000 0x10000>,
1166			      <0x38880000 0xc0000>;
1167			#interrupt-cells = <3>;
1168			interrupt-controller;
1169			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1170		};
1171
1172		ddrc: memory-controller@3d400000 {
1173			compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1174			reg = <0x3d400000 0x400000>;
1175			clock-names = "core", "pll", "alt", "apb";
1176			clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1177				 <&clk IMX8MN_DRAM_PLL>,
1178				 <&clk IMX8MN_CLK_DRAM_ALT>,
1179				 <&clk IMX8MN_CLK_DRAM_APB>;
1180		};
1181
1182		ddr-pmu@3d800000 {
1183			compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1184			reg = <0x3d800000 0x400000>;
1185			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1186		};
1187	};
1188
1189	usbphynop1: usbphynop1 {
1190		#phy-cells = <0>;
1191		compatible = "usb-nop-xceiv";
1192		clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1193		assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1194		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1195		clock-names = "main_clk";
1196		power-domains = <&pgc_otg1>;
1197	};
1198};
1199