1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/power/imx8mn-power.h>
8#include <dt-bindings/reset/imx8mq-reset.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/thermal/thermal.h>
13
14#include "imx8mn-pinfunc.h"
15
16/ {
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		ethernet0 = &fec1;
23		gpio0 = &gpio1;
24		gpio1 = &gpio2;
25		gpio2 = &gpio3;
26		gpio3 = &gpio4;
27		gpio4 = &gpio5;
28		i2c0 = &i2c1;
29		i2c1 = &i2c2;
30		i2c2 = &i2c3;
31		i2c3 = &i2c4;
32		mmc0 = &usdhc1;
33		mmc1 = &usdhc2;
34		mmc2 = &usdhc3;
35		serial0 = &uart1;
36		serial1 = &uart2;
37		serial2 = &uart3;
38		serial3 = &uart4;
39		spi0 = &ecspi1;
40		spi1 = &ecspi2;
41		spi2 = &ecspi3;
42	};
43
44	cpus {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		idle-states {
49			entry-method = "psci";
50
51			cpu_pd_wait: cpu-pd-wait {
52				compatible = "arm,idle-state";
53				arm,psci-suspend-param = <0x0010033>;
54				local-timer-stop;
55				entry-latency-us = <1000>;
56				exit-latency-us = <700>;
57				min-residency-us = <2700>;
58			};
59		};
60
61		A53_0: cpu@0 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a53";
64			reg = <0x0>;
65			clock-latency = <61036>;
66			clocks = <&clk IMX8MN_CLK_ARM>;
67			enable-method = "psci";
68			i-cache-size = <0x8000>;
69			i-cache-line-size = <64>;
70			i-cache-sets = <256>;
71			d-cache-size = <0x8000>;
72			d-cache-line-size = <64>;
73			d-cache-sets = <128>;
74			next-level-cache = <&A53_L2>;
75			operating-points-v2 = <&a53_opp_table>;
76			nvmem-cells = <&cpu_speed_grade>;
77			nvmem-cell-names = "speed_grade";
78			cpu-idle-states = <&cpu_pd_wait>;
79			#cooling-cells = <2>;
80		};
81
82		A53_1: cpu@1 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			reg = <0x1>;
86			clock-latency = <61036>;
87			clocks = <&clk IMX8MN_CLK_ARM>;
88			enable-method = "psci";
89			i-cache-size = <0x8000>;
90			i-cache-line-size = <64>;
91			i-cache-sets = <256>;
92			d-cache-size = <0x8000>;
93			d-cache-line-size = <64>;
94			d-cache-sets = <128>;
95			next-level-cache = <&A53_L2>;
96			operating-points-v2 = <&a53_opp_table>;
97			cpu-idle-states = <&cpu_pd_wait>;
98			#cooling-cells = <2>;
99		};
100
101		A53_2: cpu@2 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a53";
104			reg = <0x2>;
105			clock-latency = <61036>;
106			clocks = <&clk IMX8MN_CLK_ARM>;
107			enable-method = "psci";
108			i-cache-size = <0x8000>;
109			i-cache-line-size = <64>;
110			i-cache-sets = <256>;
111			d-cache-size = <0x8000>;
112			d-cache-line-size = <64>;
113			d-cache-sets = <128>;
114			next-level-cache = <&A53_L2>;
115			operating-points-v2 = <&a53_opp_table>;
116			cpu-idle-states = <&cpu_pd_wait>;
117			#cooling-cells = <2>;
118		};
119
120		A53_3: cpu@3 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a53";
123			reg = <0x3>;
124			clock-latency = <61036>;
125			clocks = <&clk IMX8MN_CLK_ARM>;
126			enable-method = "psci";
127			i-cache-size = <0x8000>;
128			i-cache-line-size = <64>;
129			i-cache-sets = <256>;
130			d-cache-size = <0x8000>;
131			d-cache-line-size = <64>;
132			d-cache-sets = <128>;
133			next-level-cache = <&A53_L2>;
134			operating-points-v2 = <&a53_opp_table>;
135			cpu-idle-states = <&cpu_pd_wait>;
136			#cooling-cells = <2>;
137		};
138
139		A53_L2: l2-cache0 {
140			compatible = "cache";
141			cache-level = <2>;
142			cache-size = <0x80000>;
143			cache-line-size = <64>;
144			cache-sets = <512>;
145		};
146	};
147
148	a53_opp_table: opp-table {
149		compatible = "operating-points-v2";
150		opp-shared;
151
152		opp-1200000000 {
153			opp-hz = /bits/ 64 <1200000000>;
154			opp-microvolt = <850000>;
155			opp-supported-hw = <0xb00>, <0x7>;
156			clock-latency-ns = <150000>;
157			opp-suspend;
158		};
159
160		opp-1400000000 {
161			opp-hz = /bits/ 64 <1400000000>;
162			opp-microvolt = <950000>;
163			opp-supported-hw = <0x300>, <0x7>;
164			clock-latency-ns = <150000>;
165			opp-suspend;
166		};
167
168		opp-1500000000 {
169			opp-hz = /bits/ 64 <1500000000>;
170			opp-microvolt = <1000000>;
171			opp-supported-hw = <0x100>, <0x3>;
172			clock-latency-ns = <150000>;
173			opp-suspend;
174		};
175	};
176
177	osc_32k: clock-osc-32k {
178		compatible = "fixed-clock";
179		#clock-cells = <0>;
180		clock-frequency = <32768>;
181		clock-output-names = "osc_32k";
182	};
183
184	osc_24m: clock-osc-24m {
185		compatible = "fixed-clock";
186		#clock-cells = <0>;
187		clock-frequency = <24000000>;
188		clock-output-names = "osc_24m";
189	};
190
191	clk_ext1: clock-ext1 {
192		compatible = "fixed-clock";
193		#clock-cells = <0>;
194		clock-frequency = <133000000>;
195		clock-output-names = "clk_ext1";
196	};
197
198	clk_ext2: clock-ext2 {
199		compatible = "fixed-clock";
200		#clock-cells = <0>;
201		clock-frequency = <133000000>;
202		clock-output-names = "clk_ext2";
203	};
204
205	clk_ext3: clock-ext3 {
206		compatible = "fixed-clock";
207		#clock-cells = <0>;
208		clock-frequency = <133000000>;
209		clock-output-names = "clk_ext3";
210	};
211
212	clk_ext4: clock-ext4 {
213		compatible = "fixed-clock";
214		#clock-cells = <0>;
215		clock-frequency = <133000000>;
216		clock-output-names = "clk_ext4";
217	};
218
219	pmu {
220		compatible = "arm,cortex-a53-pmu";
221		interrupts = <GIC_PPI 7
222			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
223	};
224
225	psci {
226		compatible = "arm,psci-1.0";
227		method = "smc";
228	};
229
230	thermal-zones {
231		cpu-thermal {
232			polling-delay-passive = <250>;
233			polling-delay = <2000>;
234			thermal-sensors = <&tmu>;
235			trips {
236				cpu_alert0: trip0 {
237					temperature = <85000>;
238					hysteresis = <2000>;
239					type = "passive";
240				};
241
242				cpu_crit0: trip1 {
243					temperature = <95000>;
244					hysteresis = <2000>;
245					type = "critical";
246				};
247			};
248
249			cooling-maps {
250				map0 {
251					trip = <&cpu_alert0>;
252					cooling-device =
253						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
254						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
257				};
258			};
259		};
260	};
261
262	timer {
263		compatible = "arm,armv8-timer";
264		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
265			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
266			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
267			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
268		clock-frequency = <8000000>;
269		arm,no-tick-in-suspend;
270	};
271
272	soc: soc@0 {
273		compatible = "fsl,imx8mn-soc", "simple-bus";
274		#address-cells = <1>;
275		#size-cells = <1>;
276		ranges = <0x0 0x0 0x0 0x3e000000>;
277		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
278		nvmem-cells = <&imx8mn_uid>;
279		nvmem-cell-names = "soc_unique_id";
280
281		aips1: bus@30000000 {
282			compatible = "fsl,aips-bus", "simple-bus";
283			reg = <0x30000000 0x400000>;
284			#address-cells = <1>;
285			#size-cells = <1>;
286			ranges;
287
288			spba2: spba-bus@30000000 {
289				compatible = "fsl,spba-bus", "simple-bus";
290				#address-cells = <1>;
291				#size-cells = <1>;
292				reg = <0x30000000 0x100000>;
293				ranges;
294
295				sai2: sai@30020000 {
296					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
297					reg = <0x30020000 0x10000>;
298					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
299					clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
300						<&clk IMX8MN_CLK_DUMMY>,
301						<&clk IMX8MN_CLK_SAI2_ROOT>,
302						<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
303					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
304					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
305					dma-names = "rx", "tx";
306					status = "disabled";
307				};
308
309				sai3: sai@30030000 {
310					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
311					reg = <0x30030000 0x10000>;
312					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
313					clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
314						 <&clk IMX8MN_CLK_DUMMY>,
315						 <&clk IMX8MN_CLK_SAI3_ROOT>,
316						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
317					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
318					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
319					dma-names = "rx", "tx";
320					status = "disabled";
321				};
322
323				sai5: sai@30050000 {
324					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
325					reg = <0x30050000 0x10000>;
326					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
327					clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
328						 <&clk IMX8MN_CLK_DUMMY>,
329						 <&clk IMX8MN_CLK_SAI5_ROOT>,
330						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
331					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
332					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
333					dma-names = "rx", "tx";
334					fsl,shared-interrupt;
335					fsl,dataline = <0 0xf 0xf>;
336					status = "disabled";
337				};
338
339				sai6: sai@30060000 {
340					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
341					reg = <0x30060000  0x10000>;
342					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
343					clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
344						 <&clk IMX8MN_CLK_DUMMY>,
345						 <&clk IMX8MN_CLK_SAI6_ROOT>,
346						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
347					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
348					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
349					dma-names = "rx", "tx";
350					status = "disabled";
351				};
352
353				micfil: audio-controller@30080000 {
354					compatible = "fsl,imx8mm-micfil";
355					reg = <0x30080000 0x10000>;
356					interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
357						     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
358						     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
359						     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
360					clocks = <&clk IMX8MN_CLK_PDM_IPG>,
361						 <&clk IMX8MN_CLK_PDM_ROOT>,
362						 <&clk IMX8MN_AUDIO_PLL1_OUT>,
363						 <&clk IMX8MN_AUDIO_PLL2_OUT>,
364						 <&clk IMX8MN_CLK_EXT3>;
365					clock-names = "ipg_clk", "ipg_clk_app",
366						      "pll8k", "pll11k", "clkext3";
367					dmas = <&sdma2 24 25 0x80000000>;
368					dma-names = "rx";
369					status = "disabled";
370				};
371
372				spdif1: spdif@30090000 {
373					compatible = "fsl,imx35-spdif";
374					reg = <0x30090000 0x10000>;
375					interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
376					clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
377						 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
378						 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
379						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
380						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
381						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
382						 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
383						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
384						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
385						 <&clk IMX8MN_CLK_DUMMY>; /* spba */
386					clock-names = "core", "rxtx0",
387						      "rxtx1", "rxtx2",
388						      "rxtx3", "rxtx4",
389						      "rxtx5", "rxtx6",
390						      "rxtx7", "spba";
391					dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
392					dma-names = "rx", "tx";
393					status = "disabled";
394				};
395
396				sai7: sai@300b0000 {
397					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
398					reg = <0x300b0000 0x10000>;
399					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
400					clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
401						 <&clk IMX8MN_CLK_DUMMY>,
402						 <&clk IMX8MN_CLK_SAI7_ROOT>,
403						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
404					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
405					dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
406					dma-names = "rx", "tx";
407					status = "disabled";
408				};
409
410				easrc: easrc@300c0000 {
411					compatible = "fsl,imx8mn-easrc";
412					reg = <0x300c0000 0x10000>;
413					interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
414					clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
415					clock-names = "mem";
416					dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
417					       <&sdma2 18 23 0> , <&sdma2 19 23 0>,
418					       <&sdma2 20 23 0> , <&sdma2 21 23 0>,
419					       <&sdma2 22 23 0> , <&sdma2 23 23 0>;
420					dma-names = "ctx0_rx", "ctx0_tx",
421						    "ctx1_rx", "ctx1_tx",
422						    "ctx2_rx", "ctx2_tx",
423						    "ctx3_rx", "ctx3_tx";
424					firmware-name = "imx/easrc/easrc-imx8mn.bin";
425					fsl,asrc-rate = <8000>;
426					fsl,asrc-format = <2>;
427					status = "disabled";
428				};
429			};
430
431			gpio1: gpio@30200000 {
432				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
433				reg = <0x30200000 0x10000>;
434				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
435					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436				clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
437				gpio-controller;
438				#gpio-cells = <2>;
439				interrupt-controller;
440				#interrupt-cells = <2>;
441				gpio-ranges = <&iomuxc 0 10 30>;
442			};
443
444			gpio2: gpio@30210000 {
445				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
446				reg = <0x30210000 0x10000>;
447				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
448					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449				clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
450				gpio-controller;
451				#gpio-cells = <2>;
452				interrupt-controller;
453				#interrupt-cells = <2>;
454				gpio-ranges = <&iomuxc 0 40 21>;
455			};
456
457			gpio3: gpio@30220000 {
458				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
459				reg = <0x30220000 0x10000>;
460				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
461					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
462				clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
463				gpio-controller;
464				#gpio-cells = <2>;
465				interrupt-controller;
466				#interrupt-cells = <2>;
467				gpio-ranges = <&iomuxc 0 61 26>;
468			};
469
470			gpio4: gpio@30230000 {
471				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
472				reg = <0x30230000 0x10000>;
473				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
474					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
475				clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
476				gpio-controller;
477				#gpio-cells = <2>;
478				interrupt-controller;
479				#interrupt-cells = <2>;
480				gpio-ranges = <&iomuxc 21 108 11>;
481			};
482
483			gpio5: gpio@30240000 {
484				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
485				reg = <0x30240000 0x10000>;
486				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488				clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
489				gpio-controller;
490				#gpio-cells = <2>;
491				interrupt-controller;
492				#interrupt-cells = <2>;
493				gpio-ranges = <&iomuxc 0 119 30>;
494			};
495
496			tmu: tmu@30260000 {
497				compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
498				reg = <0x30260000 0x10000>;
499				clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
500				#thermal-sensor-cells = <0>;
501			};
502
503			wdog1: watchdog@30280000 {
504				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
505				reg = <0x30280000 0x10000>;
506				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
507				clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
508				status = "disabled";
509			};
510
511			wdog2: watchdog@30290000 {
512				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
513				reg = <0x30290000 0x10000>;
514				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
515				clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
516				status = "disabled";
517			};
518
519			wdog3: watchdog@302a0000 {
520				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
521				reg = <0x302a0000 0x10000>;
522				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
523				clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
524				status = "disabled";
525			};
526
527			sdma3: dma-controller@302b0000 {
528				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
529				reg = <0x302b0000 0x10000>;
530				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
531				clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
532				 <&clk IMX8MN_CLK_SDMA3_ROOT>;
533				clock-names = "ipg", "ahb";
534				#dma-cells = <3>;
535				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
536			};
537
538			sdma2: dma-controller@302c0000 {
539				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
540				reg = <0x302c0000 0x10000>;
541				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
542				clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
543					 <&clk IMX8MN_CLK_SDMA2_ROOT>;
544				clock-names = "ipg", "ahb";
545				#dma-cells = <3>;
546				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
547			};
548
549			iomuxc: pinctrl@30330000 {
550				compatible = "fsl,imx8mn-iomuxc";
551				reg = <0x30330000 0x10000>;
552			};
553
554			gpr: iomuxc-gpr@30340000 {
555				compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
556				reg = <0x30340000 0x10000>;
557			};
558
559			ocotp: efuse@30350000 {
560				compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
561				reg = <0x30350000 0x10000>;
562				clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
563				#address-cells = <1>;
564				#size-cells = <1>;
565
566				imx8mn_uid: unique-id@410 {
567					reg = <0x4 0x8>;
568				};
569
570				cpu_speed_grade: speed-grade@10 {
571					reg = <0x10 4>;
572				};
573
574				fec_mac_address: mac-address@90 {
575					reg = <0x90 6>;
576				};
577			};
578
579			anatop: anatop@30360000 {
580				compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
581					     "syscon";
582				reg = <0x30360000 0x10000>;
583			};
584
585			snvs: snvs@30370000 {
586				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
587				reg = <0x30370000 0x10000>;
588
589				snvs_rtc: snvs-rtc-lp {
590					compatible = "fsl,sec-v4.0-mon-rtc-lp";
591					regmap = <&snvs>;
592					offset = <0x34>;
593					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
594						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
595					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
596					clock-names = "snvs-rtc";
597				};
598
599				snvs_pwrkey: snvs-powerkey {
600					compatible = "fsl,sec-v4.0-pwrkey";
601					regmap = <&snvs>;
602					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
603					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
604					clock-names = "snvs-pwrkey";
605					linux,keycode = <KEY_POWER>;
606					wakeup-source;
607					status = "disabled";
608				};
609			};
610
611			clk: clock-controller@30380000 {
612				compatible = "fsl,imx8mn-ccm";
613				reg = <0x30380000 0x10000>;
614				#clock-cells = <1>;
615				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
616					 <&clk_ext3>, <&clk_ext4>;
617				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
618					      "clk_ext3", "clk_ext4";
619				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
620						<&clk IMX8MN_CLK_A53_CORE>,
621						<&clk IMX8MN_CLK_NOC>,
622						<&clk IMX8MN_CLK_AUDIO_AHB>,
623						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
624						<&clk IMX8MN_SYS_PLL3>,
625						<&clk IMX8MN_AUDIO_PLL1>,
626						<&clk IMX8MN_AUDIO_PLL2>;
627				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
628							 <&clk IMX8MN_ARM_PLL_OUT>,
629							 <&clk IMX8MN_SYS_PLL3_OUT>,
630							 <&clk IMX8MN_SYS_PLL1_800M>;
631				assigned-clock-rates = <0>, <0>, <0>,
632							<400000000>,
633							<400000000>,
634							<600000000>,
635							<393216000>,
636							<361267200>;
637			};
638
639			src: reset-controller@30390000 {
640				compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
641				reg = <0x30390000 0x10000>;
642				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
643				#reset-cells = <1>;
644			};
645
646			gpc: gpc@303a0000 {
647				compatible = "fsl,imx8mn-gpc";
648				reg = <0x303a0000 0x10000>;
649				interrupt-parent = <&gic>;
650				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
651
652				pgc {
653					#address-cells = <1>;
654					#size-cells = <0>;
655
656					pgc_hsiomix: power-domain@0 {
657						#power-domain-cells = <0>;
658						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
659						clocks = <&clk IMX8MN_CLK_USB_BUS>;
660					};
661
662					pgc_otg1: power-domain@1 {
663						#power-domain-cells = <0>;
664						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
665					};
666
667					pgc_gpumix: power-domain@2 {
668						#power-domain-cells = <0>;
669						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
670						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
671							 <&clk IMX8MN_CLK_GPU_SHADER>,
672							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
673							 <&clk IMX8MN_CLK_GPU_AHB>;
674					};
675
676					pgc_dispmix: power-domain@3 {
677						#power-domain-cells = <0>;
678						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
679						clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
680							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
681					};
682
683					pgc_mipi: power-domain@4 {
684						#power-domain-cells = <0>;
685						reg = <IMX8MN_POWER_DOMAIN_MIPI>;
686						power-domains = <&pgc_dispmix>;
687					};
688				};
689			};
690		};
691
692		aips2: bus@30400000 {
693			compatible = "fsl,aips-bus", "simple-bus";
694			reg = <0x30400000 0x400000>;
695			#address-cells = <1>;
696			#size-cells = <1>;
697			ranges;
698
699			pwm1: pwm@30660000 {
700				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
701				reg = <0x30660000 0x10000>;
702				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
703				clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
704					<&clk IMX8MN_CLK_PWM1_ROOT>;
705				clock-names = "ipg", "per";
706				#pwm-cells = <3>;
707				status = "disabled";
708			};
709
710			pwm2: pwm@30670000 {
711				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
712				reg = <0x30670000 0x10000>;
713				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
714				clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
715					 <&clk IMX8MN_CLK_PWM2_ROOT>;
716				clock-names = "ipg", "per";
717				#pwm-cells = <3>;
718				status = "disabled";
719			};
720
721			pwm3: pwm@30680000 {
722				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
723				reg = <0x30680000 0x10000>;
724				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
725				clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
726					 <&clk IMX8MN_CLK_PWM3_ROOT>;
727				clock-names = "ipg", "per";
728				#pwm-cells = <3>;
729				status = "disabled";
730			};
731
732			pwm4: pwm@30690000 {
733				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
734				reg = <0x30690000 0x10000>;
735				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
736				clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
737					 <&clk IMX8MN_CLK_PWM4_ROOT>;
738				clock-names = "ipg", "per";
739				#pwm-cells = <3>;
740				status = "disabled";
741			};
742
743			system_counter: timer@306a0000 {
744				compatible = "nxp,sysctr-timer";
745				reg = <0x306a0000 0x20000>;
746				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
747				clocks = <&osc_24m>;
748				clock-names = "per";
749			};
750		};
751
752		aips3: bus@30800000 {
753			compatible = "fsl,aips-bus", "simple-bus";
754			reg = <0x30800000 0x400000>;
755			#address-cells = <1>;
756			#size-cells = <1>;
757			ranges;
758
759			spba1: spba-bus@30800000 {
760				compatible = "fsl,spba-bus", "simple-bus";
761				#address-cells = <1>;
762				#size-cells = <1>;
763				reg = <0x30800000 0x100000>;
764				ranges;
765
766				ecspi1: spi@30820000 {
767					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
768					#address-cells = <1>;
769					#size-cells = <0>;
770					reg = <0x30820000 0x10000>;
771					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
772					clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
773						 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
774					clock-names = "ipg", "per";
775					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
776					dma-names = "rx", "tx";
777					status = "disabled";
778				};
779
780				ecspi2: spi@30830000 {
781					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
782					#address-cells = <1>;
783					#size-cells = <0>;
784					reg = <0x30830000 0x10000>;
785					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
786					clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
787						 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
788					clock-names = "ipg", "per";
789					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
790					dma-names = "rx", "tx";
791					status = "disabled";
792				};
793
794				ecspi3: spi@30840000 {
795					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
796					#address-cells = <1>;
797					#size-cells = <0>;
798					reg = <0x30840000 0x10000>;
799					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
800					clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
801						 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
802					clock-names = "ipg", "per";
803					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
804					dma-names = "rx", "tx";
805					status = "disabled";
806				};
807
808				uart1: serial@30860000 {
809					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
810					reg = <0x30860000 0x10000>;
811					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
812					clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
813						 <&clk IMX8MN_CLK_UART1_ROOT>;
814					clock-names = "ipg", "per";
815					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
816					dma-names = "rx", "tx";
817					status = "disabled";
818				};
819
820				uart3: serial@30880000 {
821					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
822					reg = <0x30880000 0x10000>;
823					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
824					clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
825						 <&clk IMX8MN_CLK_UART3_ROOT>;
826					clock-names = "ipg", "per";
827					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
828					dma-names = "rx", "tx";
829					status = "disabled";
830				};
831
832				uart2: serial@30890000 {
833					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
834					reg = <0x30890000 0x10000>;
835					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
836					clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
837						 <&clk IMX8MN_CLK_UART2_ROOT>;
838					clock-names = "ipg", "per";
839					status = "disabled";
840				};
841			};
842
843			crypto: crypto@30900000 {
844				compatible = "fsl,sec-v4.0";
845				#address-cells = <1>;
846				#size-cells = <1>;
847				reg = <0x30900000 0x40000>;
848				ranges = <0 0x30900000 0x40000>;
849				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
850				clocks = <&clk IMX8MN_CLK_AHB>,
851					 <&clk IMX8MN_CLK_IPG_ROOT>;
852				clock-names = "aclk", "ipg";
853
854				sec_jr0: jr@1000 {
855					 compatible = "fsl,sec-v4.0-job-ring";
856					 reg = <0x1000 0x1000>;
857					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
858					 status = "disabled";
859				};
860
861				sec_jr1: jr@2000 {
862					 compatible = "fsl,sec-v4.0-job-ring";
863					 reg = <0x2000 0x1000>;
864					 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
865				};
866
867				sec_jr2: jr@3000 {
868					 compatible = "fsl,sec-v4.0-job-ring";
869					 reg = <0x3000 0x1000>;
870					 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
871				};
872			};
873
874			i2c1: i2c@30a20000 {
875				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
876				#address-cells = <1>;
877				#size-cells = <0>;
878				reg = <0x30a20000 0x10000>;
879				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
880				clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
881				status = "disabled";
882			};
883
884			i2c2: i2c@30a30000 {
885				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
886				#address-cells = <1>;
887				#size-cells = <0>;
888				reg = <0x30a30000 0x10000>;
889				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
890				clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
891				status = "disabled";
892			};
893
894			i2c3: i2c@30a40000 {
895				#address-cells = <1>;
896				#size-cells = <0>;
897				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
898				reg = <0x30a40000 0x10000>;
899				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
900				clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
901				status = "disabled";
902			};
903
904			i2c4: i2c@30a50000 {
905				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
906				#address-cells = <1>;
907				#size-cells = <0>;
908				reg = <0x30a50000 0x10000>;
909				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
910				clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
911				status = "disabled";
912			};
913
914			uart4: serial@30a60000 {
915				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
916				reg = <0x30a60000 0x10000>;
917				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
918				clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
919					 <&clk IMX8MN_CLK_UART4_ROOT>;
920				clock-names = "ipg", "per";
921				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
922				dma-names = "rx", "tx";
923				status = "disabled";
924			};
925
926			mu: mailbox@30aa0000 {
927				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
928				reg = <0x30aa0000 0x10000>;
929				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
930				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
931				#mbox-cells = <2>;
932			};
933
934			usdhc1: mmc@30b40000 {
935				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
936				reg = <0x30b40000 0x10000>;
937				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
938				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
939					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
940					 <&clk IMX8MN_CLK_USDHC1_ROOT>;
941				clock-names = "ipg", "ahb", "per";
942				fsl,tuning-start-tap = <20>;
943				fsl,tuning-step = <2>;
944				bus-width = <4>;
945				status = "disabled";
946			};
947
948			usdhc2: mmc@30b50000 {
949				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
950				reg = <0x30b50000 0x10000>;
951				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
952				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
953					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
954					 <&clk IMX8MN_CLK_USDHC2_ROOT>;
955				clock-names = "ipg", "ahb", "per";
956				fsl,tuning-start-tap = <20>;
957				fsl,tuning-step = <2>;
958				bus-width = <4>;
959				status = "disabled";
960			};
961
962			usdhc3: mmc@30b60000 {
963				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
964				reg = <0x30b60000 0x10000>;
965				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
966				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
967					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
968					 <&clk IMX8MN_CLK_USDHC3_ROOT>;
969				clock-names = "ipg", "ahb", "per";
970				fsl,tuning-start-tap = <20>;
971				fsl,tuning-step = <2>;
972				bus-width = <4>;
973				status = "disabled";
974			};
975
976			flexspi: spi@30bb0000 {
977				#address-cells = <1>;
978				#size-cells = <0>;
979				compatible = "nxp,imx8mm-fspi";
980				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
981				reg-names = "fspi_base", "fspi_mmap";
982				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
983				clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
984					 <&clk IMX8MN_CLK_QSPI_ROOT>;
985				clock-names = "fspi_en", "fspi";
986				status = "disabled";
987			};
988
989			sdma1: dma-controller@30bd0000 {
990				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
991				reg = <0x30bd0000 0x10000>;
992				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
993				clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
994					 <&clk IMX8MN_CLK_AHB>;
995				clock-names = "ipg", "ahb";
996				#dma-cells = <3>;
997				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
998			};
999
1000			fec1: ethernet@30be0000 {
1001				compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1002				reg = <0x30be0000 0x10000>;
1003				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1004					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1005					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1006					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1007				clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
1008					 <&clk IMX8MN_CLK_ENET1_ROOT>,
1009					 <&clk IMX8MN_CLK_ENET_TIMER>,
1010					 <&clk IMX8MN_CLK_ENET_REF>,
1011					 <&clk IMX8MN_CLK_ENET_PHY_REF>;
1012				clock-names = "ipg", "ahb", "ptp",
1013					      "enet_clk_ref", "enet_out";
1014				assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1015						  <&clk IMX8MN_CLK_ENET_TIMER>,
1016						  <&clk IMX8MN_CLK_ENET_REF>,
1017						  <&clk IMX8MN_CLK_ENET_PHY_REF>;
1018				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1019							 <&clk IMX8MN_SYS_PLL2_100M>,
1020							 <&clk IMX8MN_SYS_PLL2_125M>,
1021							 <&clk IMX8MN_SYS_PLL2_50M>;
1022				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1023				fsl,num-tx-queues = <3>;
1024				fsl,num-rx-queues = <3>;
1025				nvmem-cells = <&fec_mac_address>;
1026				nvmem-cell-names = "mac-address";
1027				fsl,stop-mode = <&gpr 0x10 3>;
1028				status = "disabled";
1029			};
1030
1031		};
1032
1033		aips4: bus@32c00000 {
1034			compatible = "fsl,aips-bus", "simple-bus";
1035			reg = <0x32c00000 0x400000>;
1036			#address-cells = <1>;
1037			#size-cells = <1>;
1038			ranges;
1039
1040			disp_blk_ctrl: blk-ctrl@32e28000 {
1041				compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1042				reg = <0x32e28000 0x100>;
1043				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1044						<&pgc_dispmix>, <&pgc_mipi>,
1045						<&pgc_mipi>;
1046				power-domain-names = "bus", "isi",
1047						     "lcdif", "mipi-dsi",
1048						     "mipi-csi";
1049				clocks = <&clk IMX8MN_CLK_DISP_AXI>,
1050					 <&clk IMX8MN_CLK_DISP_APB>,
1051					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1052					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1053					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
1054					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
1055					 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
1056					 <&clk IMX8MN_CLK_DSI_CORE>,
1057					 <&clk IMX8MN_CLK_DSI_PHY_REF>,
1058					 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
1059					 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
1060				clock-names = "disp_axi", "disp_apb",
1061					      "disp_axi_root", "disp_apb_root",
1062					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
1063					      "dsi-pclk", "dsi-ref",
1064					      "csi-aclk", "csi-pclk";
1065				#power-domain-cells = <1>;
1066			};
1067
1068			usbotg1: usb@32e40000 {
1069				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
1070				reg = <0x32e40000 0x200>;
1071				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1072				clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
1073				clock-names = "usb1_ctrl_root_clk";
1074				assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1075				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1076				phys = <&usbphynop1>;
1077				fsl,usbmisc = <&usbmisc1 0>;
1078				power-domains = <&pgc_hsiomix>;
1079				status = "disabled";
1080			};
1081
1082			usbmisc1: usbmisc@32e40200 {
1083				compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
1084				#index-cells = <1>;
1085				reg = <0x32e40200 0x200>;
1086			};
1087		};
1088
1089		dma_apbh: dma-controller@33000000 {
1090			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1091			reg = <0x33000000 0x2000>;
1092			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1093				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1094				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1095				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1096			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1097			#dma-cells = <1>;
1098			dma-channels = <4>;
1099			clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1100		};
1101
1102		gpmi: nand-controller@33002000 {
1103			compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1104			#address-cells = <1>;
1105			#size-cells = <1>;
1106			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1107			reg-names = "gpmi-nand", "bch";
1108			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1109			interrupt-names = "bch";
1110			clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1111				 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1112			clock-names = "gpmi_io", "gpmi_bch_apb";
1113			dmas = <&dma_apbh 0>;
1114			dma-names = "rx-tx";
1115			status = "disabled";
1116		};
1117
1118		gpu: gpu@38000000 {
1119			compatible = "vivante,gc";
1120			reg = <0x38000000 0x8000>;
1121			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1122			clocks = <&clk IMX8MN_CLK_GPU_AHB>,
1123				<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
1124				<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
1125				<&clk IMX8MN_CLK_GPU_SHADER>;
1126			clock-names = "reg", "bus", "core", "shader";
1127			assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1128					  <&clk IMX8MN_CLK_GPU_SHADER>,
1129					  <&clk IMX8MN_CLK_GPU_AXI>,
1130					  <&clk IMX8MN_CLK_GPU_AHB>,
1131					  <&clk IMX8MN_GPU_PLL>;
1132			assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1133						  <&clk IMX8MN_GPU_PLL_OUT>,
1134						  <&clk IMX8MN_SYS_PLL1_800M>,
1135						  <&clk IMX8MN_SYS_PLL1_800M>;
1136			assigned-clock-rates = <400000000>,
1137					       <400000000>,
1138					       <800000000>,
1139					       <400000000>,
1140					       <1200000000>;
1141			power-domains = <&pgc_gpumix>;
1142		};
1143
1144		gic: interrupt-controller@38800000 {
1145			compatible = "arm,gic-v3";
1146			reg = <0x38800000 0x10000>,
1147			      <0x38880000 0xc0000>;
1148			#interrupt-cells = <3>;
1149			interrupt-controller;
1150			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1151		};
1152
1153		ddrc: memory-controller@3d400000 {
1154			compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1155			reg = <0x3d400000 0x400000>;
1156			clock-names = "core", "pll", "alt", "apb";
1157			clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
1158				 <&clk IMX8MN_DRAM_PLL>,
1159				 <&clk IMX8MN_CLK_DRAM_ALT>,
1160				 <&clk IMX8MN_CLK_DRAM_APB>;
1161		};
1162
1163		ddr-pmu@3d800000 {
1164			compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1165			reg = <0x3d800000 0x400000>;
1166			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1167		};
1168	};
1169
1170	usbphynop1: usbphynop1 {
1171		#phy-cells = <0>;
1172		compatible = "usb-nop-xceiv";
1173		clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1174		assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1175		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1176		clock-names = "main_clk";
1177		power-domains = <&pgc_otg1>;
1178	};
1179};
1180