1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; 66 clocks = <&clk IMX8MN_CLK_ARM>; 67 enable-method = "psci"; 68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 75 operating-points-v2 = <&a53_opp_table>; 76 nvmem-cells = <&cpu_speed_grade>; 77 nvmem-cell-names = "speed_grade"; 78 cpu-idle-states = <&cpu_pd_wait>; 79 #cooling-cells = <2>; 80 }; 81 82 A53_1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x1>; 86 clock-latency = <61036>; 87 clocks = <&clk IMX8MN_CLK_ARM>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 cpu-idle-states = <&cpu_pd_wait>; 98 #cooling-cells = <2>; 99 }; 100 101 A53_2: cpu@2 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x2>; 105 clock-latency = <61036>; 106 clocks = <&clk IMX8MN_CLK_ARM>; 107 enable-method = "psci"; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&A53_L2>; 115 operating-points-v2 = <&a53_opp_table>; 116 cpu-idle-states = <&cpu_pd_wait>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_3: cpu@3 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x3>; 124 clock-latency = <61036>; 125 clocks = <&clk IMX8MN_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 cpu-idle-states = <&cpu_pd_wait>; 136 #cooling-cells = <2>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-level = <2>; 142 cache-unified; 143 cache-size = <0x80000>; 144 cache-line-size = <64>; 145 cache-sets = <512>; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-1200000000 { 154 opp-hz = /bits/ 64 <1200000000>; 155 opp-microvolt = <850000>; 156 opp-supported-hw = <0xb00>, <0x7>; 157 clock-latency-ns = <150000>; 158 opp-suspend; 159 }; 160 161 opp-1400000000 { 162 opp-hz = /bits/ 64 <1400000000>; 163 opp-microvolt = <950000>; 164 opp-supported-hw = <0x300>, <0x7>; 165 clock-latency-ns = <150000>; 166 opp-suspend; 167 }; 168 169 opp-1500000000 { 170 opp-hz = /bits/ 64 <1500000000>; 171 opp-microvolt = <1000000>; 172 opp-supported-hw = <0x100>, <0x3>; 173 clock-latency-ns = <150000>; 174 opp-suspend; 175 }; 176 }; 177 178 osc_32k: clock-osc-32k { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency = <32768>; 182 clock-output-names = "osc_32k"; 183 }; 184 185 osc_24m: clock-osc-24m { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <24000000>; 189 clock-output-names = "osc_24m"; 190 }; 191 192 clk_ext1: clock-ext1 { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <133000000>; 196 clock-output-names = "clk_ext1"; 197 }; 198 199 clk_ext2: clock-ext2 { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <133000000>; 203 clock-output-names = "clk_ext2"; 204 }; 205 206 clk_ext3: clock-ext3 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <133000000>; 210 clock-output-names = "clk_ext3"; 211 }; 212 213 clk_ext4: clock-ext4 { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 clock-frequency = <133000000>; 217 clock-output-names = "clk_ext4"; 218 }; 219 220 pmu { 221 compatible = "arm,cortex-a53-pmu"; 222 interrupts = <GIC_PPI 7 223 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 224 }; 225 226 psci { 227 compatible = "arm,psci-1.0"; 228 method = "smc"; 229 }; 230 231 thermal-zones { 232 cpu-thermal { 233 polling-delay-passive = <250>; 234 polling-delay = <2000>; 235 thermal-sensors = <&tmu>; 236 trips { 237 cpu_alert0: trip0 { 238 temperature = <85000>; 239 hysteresis = <2000>; 240 type = "passive"; 241 }; 242 243 cpu_crit0: trip1 { 244 temperature = <95000>; 245 hysteresis = <2000>; 246 type = "critical"; 247 }; 248 }; 249 250 cooling-maps { 251 map0 { 252 trip = <&cpu_alert0>; 253 cooling-device = 254 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 255 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 256 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 257 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 258 }; 259 }; 260 }; 261 }; 262 263 timer { 264 compatible = "arm,armv8-timer"; 265 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 266 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 267 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 268 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 269 clock-frequency = <8000000>; 270 arm,no-tick-in-suspend; 271 }; 272 273 soc: soc@0 { 274 compatible = "fsl,imx8mn-soc", "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges = <0x0 0x0 0x0 0x3e000000>; 278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 279 nvmem-cells = <&imx8mn_uid>; 280 nvmem-cell-names = "soc_unique_id"; 281 282 aips1: bus@30000000 { 283 compatible = "fsl,aips-bus", "simple-bus"; 284 reg = <0x30000000 0x400000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 spba2: spba-bus@30000000 { 290 compatible = "fsl,spba-bus", "simple-bus"; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 reg = <0x30000000 0x100000>; 294 ranges; 295 296 sai2: sai@30020000 { 297 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 298 reg = <0x30020000 0x10000>; 299 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 301 <&clk IMX8MN_CLK_DUMMY>, 302 <&clk IMX8MN_CLK_SAI2_ROOT>, 303 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 304 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 305 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 306 dma-names = "rx", "tx"; 307 status = "disabled"; 308 }; 309 310 sai3: sai@30030000 { 311 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 312 reg = <0x30030000 0x10000>; 313 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 315 <&clk IMX8MN_CLK_DUMMY>, 316 <&clk IMX8MN_CLK_SAI3_ROOT>, 317 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 318 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 319 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 }; 323 324 sai5: sai@30050000 { 325 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 326 reg = <0x30050000 0x10000>; 327 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 329 <&clk IMX8MN_CLK_DUMMY>, 330 <&clk IMX8MN_CLK_SAI5_ROOT>, 331 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 332 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 333 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 334 dma-names = "rx", "tx"; 335 fsl,shared-interrupt; 336 fsl,dataline = <0 0xf 0xf>; 337 status = "disabled"; 338 }; 339 340 sai6: sai@30060000 { 341 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 342 reg = <0x30060000 0x10000>; 343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 345 <&clk IMX8MN_CLK_DUMMY>, 346 <&clk IMX8MN_CLK_SAI6_ROOT>, 347 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 348 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 micfil: audio-controller@30080000 { 355 compatible = "fsl,imx8mm-micfil"; 356 reg = <0x30080000 0x10000>; 357 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 362 <&clk IMX8MN_CLK_PDM_ROOT>, 363 <&clk IMX8MN_AUDIO_PLL1_OUT>, 364 <&clk IMX8MN_AUDIO_PLL2_OUT>, 365 <&clk IMX8MN_CLK_EXT3>; 366 clock-names = "ipg_clk", "ipg_clk_app", 367 "pll8k", "pll11k", "clkext3"; 368 dmas = <&sdma2 24 25 0x80000000>; 369 dma-names = "rx"; 370 status = "disabled"; 371 }; 372 373 spdif1: spdif@30090000 { 374 compatible = "fsl,imx35-spdif"; 375 reg = <0x30090000 0x10000>; 376 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 378 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 379 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 380 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 382 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 383 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 386 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 387 clock-names = "core", "rxtx0", 388 "rxtx1", "rxtx2", 389 "rxtx3", "rxtx4", 390 "rxtx5", "rxtx6", 391 "rxtx7", "spba"; 392 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 393 dma-names = "rx", "tx"; 394 status = "disabled"; 395 }; 396 397 sai7: sai@300b0000 { 398 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 399 reg = <0x300b0000 0x10000>; 400 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 402 <&clk IMX8MN_CLK_DUMMY>, 403 <&clk IMX8MN_CLK_SAI7_ROOT>, 404 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 405 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 406 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 easrc: easrc@300c0000 { 412 compatible = "fsl,imx8mn-easrc"; 413 reg = <0x300c0000 0x10000>; 414 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 416 clock-names = "mem"; 417 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 418 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 419 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 420 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 421 dma-names = "ctx0_rx", "ctx0_tx", 422 "ctx1_rx", "ctx1_tx", 423 "ctx2_rx", "ctx2_tx", 424 "ctx3_rx", "ctx3_tx"; 425 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 426 fsl,asrc-rate = <8000>; 427 fsl,asrc-format = <2>; 428 status = "disabled"; 429 }; 430 }; 431 432 gpio1: gpio@30200000 { 433 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 434 reg = <0x30200000 0x10000>; 435 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 438 gpio-controller; 439 #gpio-cells = <2>; 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 gpio-ranges = <&iomuxc 0 10 30>; 443 }; 444 445 gpio2: gpio@30210000 { 446 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 447 reg = <0x30210000 0x10000>; 448 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 451 gpio-controller; 452 #gpio-cells = <2>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 gpio-ranges = <&iomuxc 0 40 21>; 456 }; 457 458 gpio3: gpio@30220000 { 459 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 460 reg = <0x30220000 0x10000>; 461 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 464 gpio-controller; 465 #gpio-cells = <2>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 gpio-ranges = <&iomuxc 0 61 26>; 469 }; 470 471 gpio4: gpio@30230000 { 472 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 473 reg = <0x30230000 0x10000>; 474 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 gpio-ranges = <&iomuxc 21 108 11>; 482 }; 483 484 gpio5: gpio@30240000 { 485 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 486 reg = <0x30240000 0x10000>; 487 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 490 gpio-controller; 491 #gpio-cells = <2>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 gpio-ranges = <&iomuxc 0 119 30>; 495 }; 496 497 tmu: tmu@30260000 { 498 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 499 reg = <0x30260000 0x10000>; 500 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 501 #thermal-sensor-cells = <0>; 502 }; 503 504 wdog1: watchdog@30280000 { 505 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 506 reg = <0x30280000 0x10000>; 507 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 509 status = "disabled"; 510 }; 511 512 wdog2: watchdog@30290000 { 513 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 514 reg = <0x30290000 0x10000>; 515 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 517 status = "disabled"; 518 }; 519 520 wdog3: watchdog@302a0000 { 521 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 522 reg = <0x302a0000 0x10000>; 523 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 525 status = "disabled"; 526 }; 527 528 sdma3: dma-controller@302b0000 { 529 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 530 reg = <0x302b0000 0x10000>; 531 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 533 <&clk IMX8MN_CLK_SDMA3_ROOT>; 534 clock-names = "ipg", "ahb"; 535 #dma-cells = <3>; 536 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 537 }; 538 539 sdma2: dma-controller@302c0000 { 540 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 541 reg = <0x302c0000 0x10000>; 542 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 544 <&clk IMX8MN_CLK_SDMA2_ROOT>; 545 clock-names = "ipg", "ahb"; 546 #dma-cells = <3>; 547 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 548 }; 549 550 iomuxc: pinctrl@30330000 { 551 compatible = "fsl,imx8mn-iomuxc"; 552 reg = <0x30330000 0x10000>; 553 }; 554 555 gpr: iomuxc-gpr@30340000 { 556 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 557 reg = <0x30340000 0x10000>; 558 }; 559 560 ocotp: efuse@30350000 { 561 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 562 reg = <0x30350000 0x10000>; 563 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 564 #address-cells = <1>; 565 #size-cells = <1>; 566 567 imx8mn_uid: unique-id@410 { 568 reg = <0x4 0x8>; 569 }; 570 571 cpu_speed_grade: speed-grade@10 { 572 reg = <0x10 4>; 573 }; 574 575 fec_mac_address: mac-address@90 { 576 reg = <0x90 6>; 577 }; 578 }; 579 580 anatop: clock-controller@30360000 { 581 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; 582 reg = <0x30360000 0x10000>; 583 #clock-cells = <1>; 584 }; 585 586 snvs: snvs@30370000 { 587 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 588 reg = <0x30370000 0x10000>; 589 590 snvs_rtc: snvs-rtc-lp { 591 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 592 regmap = <&snvs>; 593 offset = <0x34>; 594 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 597 clock-names = "snvs-rtc"; 598 }; 599 600 snvs_pwrkey: snvs-powerkey { 601 compatible = "fsl,sec-v4.0-pwrkey"; 602 regmap = <&snvs>; 603 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 605 clock-names = "snvs-pwrkey"; 606 linux,keycode = <KEY_POWER>; 607 wakeup-source; 608 status = "disabled"; 609 }; 610 }; 611 612 clk: clock-controller@30380000 { 613 compatible = "fsl,imx8mn-ccm"; 614 reg = <0x30380000 0x10000>; 615 #clock-cells = <1>; 616 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 617 <&clk_ext3>, <&clk_ext4>; 618 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 619 "clk_ext3", "clk_ext4"; 620 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 621 <&clk IMX8MN_CLK_A53_CORE>, 622 <&clk IMX8MN_CLK_NOC>, 623 <&clk IMX8MN_CLK_AUDIO_AHB>, 624 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 625 <&clk IMX8MN_SYS_PLL3>, 626 <&clk IMX8MN_AUDIO_PLL1>, 627 <&clk IMX8MN_AUDIO_PLL2>; 628 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 629 <&clk IMX8MN_ARM_PLL_OUT>, 630 <&clk IMX8MN_SYS_PLL3_OUT>, 631 <&clk IMX8MN_SYS_PLL1_800M>; 632 assigned-clock-rates = <0>, <0>, <0>, 633 <400000000>, 634 <400000000>, 635 <600000000>, 636 <393216000>, 637 <361267200>; 638 }; 639 640 src: reset-controller@30390000 { 641 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 642 reg = <0x30390000 0x10000>; 643 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 644 #reset-cells = <1>; 645 }; 646 647 gpc: gpc@303a0000 { 648 compatible = "fsl,imx8mn-gpc"; 649 reg = <0x303a0000 0x10000>; 650 interrupt-parent = <&gic>; 651 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 652 653 pgc { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 657 pgc_hsiomix: power-domain@0 { 658 #power-domain-cells = <0>; 659 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 660 clocks = <&clk IMX8MN_CLK_USB_BUS>; 661 }; 662 663 pgc_otg1: power-domain@1 { 664 #power-domain-cells = <0>; 665 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 666 power-domains = <&pgc_hsiomix>; 667 }; 668 669 pgc_gpumix: power-domain@2 { 670 #power-domain-cells = <0>; 671 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 672 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 673 <&clk IMX8MN_CLK_GPU_SHADER>, 674 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 675 <&clk IMX8MN_CLK_GPU_AHB>; 676 }; 677 678 pgc_dispmix: power-domain@3 { 679 #power-domain-cells = <0>; 680 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 681 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 682 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 683 }; 684 685 pgc_mipi: power-domain@4 { 686 #power-domain-cells = <0>; 687 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 688 power-domains = <&pgc_dispmix>; 689 }; 690 }; 691 }; 692 }; 693 694 aips2: bus@30400000 { 695 compatible = "fsl,aips-bus", "simple-bus"; 696 reg = <0x30400000 0x400000>; 697 #address-cells = <1>; 698 #size-cells = <1>; 699 ranges; 700 701 pwm1: pwm@30660000 { 702 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 703 reg = <0x30660000 0x10000>; 704 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 706 <&clk IMX8MN_CLK_PWM1_ROOT>; 707 clock-names = "ipg", "per"; 708 #pwm-cells = <3>; 709 status = "disabled"; 710 }; 711 712 pwm2: pwm@30670000 { 713 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 714 reg = <0x30670000 0x10000>; 715 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 717 <&clk IMX8MN_CLK_PWM2_ROOT>; 718 clock-names = "ipg", "per"; 719 #pwm-cells = <3>; 720 status = "disabled"; 721 }; 722 723 pwm3: pwm@30680000 { 724 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 725 reg = <0x30680000 0x10000>; 726 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 728 <&clk IMX8MN_CLK_PWM3_ROOT>; 729 clock-names = "ipg", "per"; 730 #pwm-cells = <3>; 731 status = "disabled"; 732 }; 733 734 pwm4: pwm@30690000 { 735 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 736 reg = <0x30690000 0x10000>; 737 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 739 <&clk IMX8MN_CLK_PWM4_ROOT>; 740 clock-names = "ipg", "per"; 741 #pwm-cells = <3>; 742 status = "disabled"; 743 }; 744 745 system_counter: timer@306a0000 { 746 compatible = "nxp,sysctr-timer"; 747 reg = <0x306a0000 0x20000>; 748 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&osc_24m>; 750 clock-names = "per"; 751 }; 752 }; 753 754 aips3: bus@30800000 { 755 compatible = "fsl,aips-bus", "simple-bus"; 756 reg = <0x30800000 0x400000>; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 ranges; 760 761 spba1: spba-bus@30800000 { 762 compatible = "fsl,spba-bus", "simple-bus"; 763 #address-cells = <1>; 764 #size-cells = <1>; 765 reg = <0x30800000 0x100000>; 766 ranges; 767 768 ecspi1: spi@30820000 { 769 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 reg = <0x30820000 0x10000>; 773 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 775 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 776 clock-names = "ipg", "per"; 777 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 778 dma-names = "rx", "tx"; 779 status = "disabled"; 780 }; 781 782 ecspi2: spi@30830000 { 783 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 reg = <0x30830000 0x10000>; 787 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 789 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 790 clock-names = "ipg", "per"; 791 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 792 dma-names = "rx", "tx"; 793 status = "disabled"; 794 }; 795 796 ecspi3: spi@30840000 { 797 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 reg = <0x30840000 0x10000>; 801 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 803 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 804 clock-names = "ipg", "per"; 805 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 806 dma-names = "rx", "tx"; 807 status = "disabled"; 808 }; 809 810 uart1: serial@30860000 { 811 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 812 reg = <0x30860000 0x10000>; 813 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 815 <&clk IMX8MN_CLK_UART1_ROOT>; 816 clock-names = "ipg", "per"; 817 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 818 dma-names = "rx", "tx"; 819 status = "disabled"; 820 }; 821 822 uart3: serial@30880000 { 823 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 824 reg = <0x30880000 0x10000>; 825 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 827 <&clk IMX8MN_CLK_UART3_ROOT>; 828 clock-names = "ipg", "per"; 829 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 830 dma-names = "rx", "tx"; 831 status = "disabled"; 832 }; 833 834 uart2: serial@30890000 { 835 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 836 reg = <0x30890000 0x10000>; 837 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 839 <&clk IMX8MN_CLK_UART2_ROOT>; 840 clock-names = "ipg", "per"; 841 status = "disabled"; 842 }; 843 }; 844 845 crypto: crypto@30900000 { 846 compatible = "fsl,sec-v4.0"; 847 #address-cells = <1>; 848 #size-cells = <1>; 849 reg = <0x30900000 0x40000>; 850 ranges = <0 0x30900000 0x40000>; 851 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&clk IMX8MN_CLK_AHB>, 853 <&clk IMX8MN_CLK_IPG_ROOT>; 854 clock-names = "aclk", "ipg"; 855 856 sec_jr0: jr@1000 { 857 compatible = "fsl,sec-v4.0-job-ring"; 858 reg = <0x1000 0x1000>; 859 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 860 status = "disabled"; 861 }; 862 863 sec_jr1: jr@2000 { 864 compatible = "fsl,sec-v4.0-job-ring"; 865 reg = <0x2000 0x1000>; 866 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 867 }; 868 869 sec_jr2: jr@3000 { 870 compatible = "fsl,sec-v4.0-job-ring"; 871 reg = <0x3000 0x1000>; 872 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 873 }; 874 }; 875 876 i2c1: i2c@30a20000 { 877 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 reg = <0x30a20000 0x10000>; 881 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 883 status = "disabled"; 884 }; 885 886 i2c2: i2c@30a30000 { 887 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 reg = <0x30a30000 0x10000>; 891 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 893 status = "disabled"; 894 }; 895 896 i2c3: i2c@30a40000 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 900 reg = <0x30a40000 0x10000>; 901 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 903 status = "disabled"; 904 }; 905 906 i2c4: i2c@30a50000 { 907 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 reg = <0x30a50000 0x10000>; 911 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 913 status = "disabled"; 914 }; 915 916 uart4: serial@30a60000 { 917 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 918 reg = <0x30a60000 0x10000>; 919 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 921 <&clk IMX8MN_CLK_UART4_ROOT>; 922 clock-names = "ipg", "per"; 923 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 924 dma-names = "rx", "tx"; 925 status = "disabled"; 926 }; 927 928 mu: mailbox@30aa0000 { 929 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 930 reg = <0x30aa0000 0x10000>; 931 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 933 #mbox-cells = <2>; 934 }; 935 936 usdhc1: mmc@30b40000 { 937 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 938 reg = <0x30b40000 0x10000>; 939 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 941 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 942 <&clk IMX8MN_CLK_USDHC1_ROOT>; 943 clock-names = "ipg", "ahb", "per"; 944 fsl,tuning-start-tap = <20>; 945 fsl,tuning-step = <2>; 946 bus-width = <4>; 947 status = "disabled"; 948 }; 949 950 usdhc2: mmc@30b50000 { 951 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 952 reg = <0x30b50000 0x10000>; 953 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 955 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 956 <&clk IMX8MN_CLK_USDHC2_ROOT>; 957 clock-names = "ipg", "ahb", "per"; 958 fsl,tuning-start-tap = <20>; 959 fsl,tuning-step = <2>; 960 bus-width = <4>; 961 status = "disabled"; 962 }; 963 964 usdhc3: mmc@30b60000 { 965 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 966 reg = <0x30b60000 0x10000>; 967 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 969 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 970 <&clk IMX8MN_CLK_USDHC3_ROOT>; 971 clock-names = "ipg", "ahb", "per"; 972 fsl,tuning-start-tap = <20>; 973 fsl,tuning-step = <2>; 974 bus-width = <4>; 975 status = "disabled"; 976 }; 977 978 flexspi: spi@30bb0000 { 979 #address-cells = <1>; 980 #size-cells = <0>; 981 compatible = "nxp,imx8mm-fspi"; 982 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 983 reg-names = "fspi_base", "fspi_mmap"; 984 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 986 <&clk IMX8MN_CLK_QSPI_ROOT>; 987 clock-names = "fspi_en", "fspi"; 988 status = "disabled"; 989 }; 990 991 sdma1: dma-controller@30bd0000 { 992 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 993 reg = <0x30bd0000 0x10000>; 994 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 996 <&clk IMX8MN_CLK_AHB>; 997 clock-names = "ipg", "ahb"; 998 #dma-cells = <3>; 999 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1000 }; 1001 1002 fec1: ethernet@30be0000 { 1003 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1004 reg = <0x30be0000 0x10000>; 1005 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 1010 <&clk IMX8MN_CLK_ENET1_ROOT>, 1011 <&clk IMX8MN_CLK_ENET_TIMER>, 1012 <&clk IMX8MN_CLK_ENET_REF>, 1013 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1014 clock-names = "ipg", "ahb", "ptp", 1015 "enet_clk_ref", "enet_out"; 1016 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 1017 <&clk IMX8MN_CLK_ENET_TIMER>, 1018 <&clk IMX8MN_CLK_ENET_REF>, 1019 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1020 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1021 <&clk IMX8MN_SYS_PLL2_100M>, 1022 <&clk IMX8MN_SYS_PLL2_125M>, 1023 <&clk IMX8MN_SYS_PLL2_50M>; 1024 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1025 fsl,num-tx-queues = <3>; 1026 fsl,num-rx-queues = <3>; 1027 nvmem-cells = <&fec_mac_address>; 1028 nvmem-cell-names = "mac-address"; 1029 fsl,stop-mode = <&gpr 0x10 3>; 1030 status = "disabled"; 1031 }; 1032 1033 }; 1034 1035 aips4: bus@32c00000 { 1036 compatible = "fsl,aips-bus", "simple-bus"; 1037 reg = <0x32c00000 0x400000>; 1038 #address-cells = <1>; 1039 #size-cells = <1>; 1040 ranges; 1041 1042 disp_blk_ctrl: blk-ctrl@32e28000 { 1043 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 1044 reg = <0x32e28000 0x100>; 1045 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1046 <&pgc_dispmix>, <&pgc_mipi>, 1047 <&pgc_mipi>; 1048 power-domain-names = "bus", "isi", 1049 "lcdif", "mipi-dsi", 1050 "mipi-csi"; 1051 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 1052 <&clk IMX8MN_CLK_DISP_APB>, 1053 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1054 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1055 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1056 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1057 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1058 <&clk IMX8MN_CLK_DSI_CORE>, 1059 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1060 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1061 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 1062 clock-names = "disp_axi", "disp_apb", 1063 "disp_axi_root", "disp_apb_root", 1064 "lcdif-axi", "lcdif-apb", "lcdif-pix", 1065 "dsi-pclk", "dsi-ref", 1066 "csi-aclk", "csi-pclk"; 1067 #power-domain-cells = <1>; 1068 }; 1069 1070 usbotg1: usb@32e40000 { 1071 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; 1072 reg = <0x32e40000 0x200>; 1073 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1075 clock-names = "usb1_ctrl_root_clk"; 1076 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1077 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1078 phys = <&usbphynop1>; 1079 fsl,usbmisc = <&usbmisc1 0>; 1080 power-domains = <&pgc_otg1>; 1081 status = "disabled"; 1082 }; 1083 1084 usbmisc1: usbmisc@32e40200 { 1085 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; 1086 #index-cells = <1>; 1087 reg = <0x32e40200 0x200>; 1088 }; 1089 }; 1090 1091 dma_apbh: dma-controller@33000000 { 1092 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1093 reg = <0x33000000 0x2000>; 1094 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1098 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1099 #dma-cells = <1>; 1100 dma-channels = <4>; 1101 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1102 }; 1103 1104 gpmi: nand-controller@33002000 { 1105 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1106 #address-cells = <1>; 1107 #size-cells = <1>; 1108 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1109 reg-names = "gpmi-nand", "bch"; 1110 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1111 interrupt-names = "bch"; 1112 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1113 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1114 clock-names = "gpmi_io", "gpmi_bch_apb"; 1115 dmas = <&dma_apbh 0>; 1116 dma-names = "rx-tx"; 1117 status = "disabled"; 1118 }; 1119 1120 gpu: gpu@38000000 { 1121 compatible = "vivante,gc"; 1122 reg = <0x38000000 0x8000>; 1123 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&clk IMX8MN_CLK_GPU_AHB>, 1125 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 1126 <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 1127 <&clk IMX8MN_CLK_GPU_SHADER>; 1128 clock-names = "reg", "bus", "core", "shader"; 1129 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, 1130 <&clk IMX8MN_CLK_GPU_SHADER>, 1131 <&clk IMX8MN_CLK_GPU_AXI>, 1132 <&clk IMX8MN_CLK_GPU_AHB>, 1133 <&clk IMX8MN_GPU_PLL>; 1134 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, 1135 <&clk IMX8MN_GPU_PLL_OUT>, 1136 <&clk IMX8MN_SYS_PLL1_800M>, 1137 <&clk IMX8MN_SYS_PLL1_800M>; 1138 assigned-clock-rates = <400000000>, 1139 <400000000>, 1140 <800000000>, 1141 <400000000>, 1142 <1200000000>; 1143 power-domains = <&pgc_gpumix>; 1144 }; 1145 1146 gic: interrupt-controller@38800000 { 1147 compatible = "arm,gic-v3"; 1148 reg = <0x38800000 0x10000>, 1149 <0x38880000 0xc0000>; 1150 #interrupt-cells = <3>; 1151 interrupt-controller; 1152 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1153 }; 1154 1155 ddrc: memory-controller@3d400000 { 1156 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1157 reg = <0x3d400000 0x400000>; 1158 clock-names = "core", "pll", "alt", "apb"; 1159 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1160 <&clk IMX8MN_DRAM_PLL>, 1161 <&clk IMX8MN_CLK_DRAM_ALT>, 1162 <&clk IMX8MN_CLK_DRAM_APB>; 1163 }; 1164 1165 ddr-pmu@3d800000 { 1166 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1167 reg = <0x3d800000 0x400000>; 1168 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1169 }; 1170 }; 1171 1172 usbphynop1: usbphynop1 { 1173 #phy-cells = <0>; 1174 compatible = "usb-nop-xceiv"; 1175 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1176 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1177 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1178 clock-names = "main_clk"; 1179 }; 1180}; 1181