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/openbmc/linux/arch/powerpc/include/asm/
H A Dsstep.h56 /* Compute flags, ORed in with type */
61 /* Branch flags, ORed in with type */
66 /* Load/store flags, ORed in with type */
72 /* Barrier type field, ORed in with type */
80 /* Cacheop values, ORed in with type */
95 /* Prefixed flag, ORed in with type */
H A Dpmac_low_i2c.h59 * direction can be directly ored in
/openbmc/linux/include/linux/regulator/
H A Dmax8973-regulator.h18 * Client need to pass this information with ORed
41 * @control_flags: Control flags which are ORed value of above flags to
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpmc.txt44 which will be ORed into PMCDR upon suspend, and cleared from PMCDR
50 first of which will be ORed into DEVDISR (and the second into
/openbmc/linux/drivers/media/i2c/
H A Dtea6420.h19 /* gain on the output pins, ORed with the output pin */
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-rapid-start10 These values are ORed together. For example, a value of 3
/openbmc/u-boot/doc/
H A DREADME.LED_display14 an ORed combination of the following values:
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dbroadcom-bcm87xx.txt12 with the existing register value, and the fourth cell is ORed with
/openbmc/linux/arch/xtensa/include/asm/
H A Dmxregs.h21 * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p
/openbmc/linux/sound/soc/fsl/
H A Dmpc5200_dma.h46 * @sicr: Base value used in serial interface control register; mode is ORed
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dcpm.txt24 - fsl,cpm-command : This value is ORed with the opcode and command flag
/openbmc/linux/Documentation/powerpc/
H A Ddexcr.rst32 aspects, which ORed with the userspace DEXCR view gives the effective DEXCR
/openbmc/linux/drivers/clk/qcom/
H A Dclk-branch.h16 * @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105_display.c65 /* Set DDRAM addr (to be ORed with exact address) */
68 /* Set CGRAM addr (to be ORed with exact address) */
/openbmc/sdbusplus/tools/sdbusplus/
H A Dmethod.py77 """Return the corresponding ORed cpp flags."""
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml23 - Software triggering (ORed with hw line)
H A Dapple,aic2.yaml21 - Software triggering (ORed with hw line)
/openbmc/linux/sound/soc/codecs/
H A Didt821034.c115 /* Power values that can be used in 'power' (can be ORed) */
158 /* Codec configuration values that can be used in 'codec_conf' (can be ORed) */
204 /* Channel direction values that can be used in 'ch_dir' (can be ORed) */
241 /* SLIC direction values that can be used in 'slic_dir' (can be ORed) */
328 /* Gain type values that can be used in 'gain_type' (cannot be ORed) */
/openbmc/linux/include/media/
H A Dcec-pin.h69 * @caps: capabilities of the CEC adapter. This will be ORed with
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-dqevent.rst148 second-oldest event is ORed with the ``changes`` field of the
178 ORed value of all the events generated.
H A Dvidioc-queryctrl.rst111 :ref:`control-id` for predefined IDs. When the ID is ORed with
189 :ref:`control-id` for predefined IDs. When the ID is ORed with
192 ID is ORed with ``V4L2_CTRL_FLAG_NEXT_COMPOUND`` the driver clears
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.h30 /* S-Video inputs consist of one luma input (In1-In8) ORed with one
52 /* Component Video inputs consist of one luma input (In1-In8) ORed
/openbmc/qemu/hw/arm/
H A Dmps2.c269 /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. in mps2_common_init()
312 /* The overflow IRQs for all UARTs are ORed together. in mps2_common_init()
313 * Tx and Rx IRQs for each UART are ORed together. in mps2_common_init()
/openbmc/linux/drivers/platform/x86/
H A Dpmc_atom.c247 * - GPIO_SUS ored dedicated IRQs in pmc_hw_reg_setup()
248 * - GPIO_SCORE ored dedicated IRQs in pmc_hw_reg_setup()
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Darm,mhu.yaml22 interrupt signal using a 32-bit register, with all 32-bits logically ORed

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