1*26a8e96aSMax Filippov /* 2*26a8e96aSMax Filippov * Xtensa MX interrupt distributor 3*26a8e96aSMax Filippov * 4*26a8e96aSMax Filippov * This file is subject to the terms and conditions of the GNU General Public 5*26a8e96aSMax Filippov * License. See the file "COPYING" in the main directory of this archive 6*26a8e96aSMax Filippov * for more details. 7*26a8e96aSMax Filippov * 8*26a8e96aSMax Filippov * Copyright (C) 2008 - 2013 Tensilica Inc. 9*26a8e96aSMax Filippov */ 10*26a8e96aSMax Filippov 11*26a8e96aSMax Filippov #ifndef _XTENSA_MXREGS_H 12*26a8e96aSMax Filippov #define _XTENSA_MXREGS_H 13*26a8e96aSMax Filippov 14*26a8e96aSMax Filippov /* 15*26a8e96aSMax Filippov * RER/WER at, as Read/write external register 16*26a8e96aSMax Filippov * at: value 17*26a8e96aSMax Filippov * as: address 18*26a8e96aSMax Filippov * 19*26a8e96aSMax Filippov * Address Value 20*26a8e96aSMax Filippov * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p 21*26a8e96aSMax Filippov * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p 22*26a8e96aSMax Filippov * 0180 0...0m..m Clear enable specified by mask (m) 23*26a8e96aSMax Filippov * 0184 0...0m..m Set enable specified by mask (m) 24*26a8e96aSMax Filippov * 0190 0...0x..x 8-bit IPI partition register 25*26a8e96aSMax Filippov * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU 26*26a8e96aSMax Filippov * V (10-bit) Release/Version 27*26a8e96aSMax Filippov * P ( 4-bit) Number of cores - 1 28*26a8e96aSMax Filippov * U (18-bit) ID 29*26a8e96aSMax Filippov * 01a0 i.......i 32-bit ConfigID 30*26a8e96aSMax Filippov * 0200 0...0m..m RunStall core 'n' 31*26a8e96aSMax Filippov * 0220 c Cache coherency enabled 32*26a8e96aSMax Filippov */ 33*26a8e96aSMax Filippov 34*26a8e96aSMax Filippov #define MIROUT(irq) (0x000 + (irq)) 35*26a8e96aSMax Filippov #define MIPICAUSE(cpu) (0x100 + (cpu)) 36*26a8e96aSMax Filippov #define MIPISET(cause) (0x140 + (cause)) 37*26a8e96aSMax Filippov #define MIENG 0x180 38*26a8e96aSMax Filippov #define MIENGSET 0x184 39*26a8e96aSMax Filippov #define MIASG 0x188 /* Read Global Assert Register */ 40*26a8e96aSMax Filippov #define MIASGSET 0x18c /* Set Global Addert Regiter */ 41*26a8e96aSMax Filippov #define MIPIPART 0x190 42*26a8e96aSMax Filippov #define SYSCFGID 0x1a0 43*26a8e96aSMax Filippov #define MPSCORE 0x200 44*26a8e96aSMax Filippov #define CCON 0x220 45*26a8e96aSMax Filippov 46*26a8e96aSMax Filippov #endif /* _XTENSA_MXREGS_H */ 47