1*0883c2c0SZhao Qiang* Freescale Communications Processor Module 2*0883c2c0SZhao Qiang 3*0883c2c0SZhao QiangNOTE: This is an interim binding, and will likely change slightly, 4*0883c2c0SZhao Qiangas more devices are supported. The QE bindings especially are 5*0883c2c0SZhao Qiangincomplete. 6*0883c2c0SZhao Qiang 7*0883c2c0SZhao Qiang* Root CPM node 8*0883c2c0SZhao Qiang 9*0883c2c0SZhao QiangProperties: 10*0883c2c0SZhao Qiang- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe". 11*0883c2c0SZhao Qiang- reg : A 48-byte region beginning with CPCR. 12*0883c2c0SZhao Qiang 13*0883c2c0SZhao QiangExample: 14*0883c2c0SZhao Qiang cpm@119c0 { 15*0883c2c0SZhao Qiang #address-cells = <1>; 16*0883c2c0SZhao Qiang #size-cells = <1>; 17*0883c2c0SZhao Qiang #interrupt-cells = <2>; 18*0883c2c0SZhao Qiang compatible = "fsl,mpc8272-cpm", "fsl,cpm2"; 19*0883c2c0SZhao Qiang reg = <119c0 30>; 20*0883c2c0SZhao Qiang } 21*0883c2c0SZhao Qiang 22*0883c2c0SZhao Qiang* Properties common to multiple CPM/QE devices 23*0883c2c0SZhao Qiang 24*0883c2c0SZhao Qiang- fsl,cpm-command : This value is ORed with the opcode and command flag 25*0883c2c0SZhao Qiang to specify the device on which a CPM command operates. 26*0883c2c0SZhao Qiang 27*0883c2c0SZhao Qiang- fsl,cpm-brg : Indicates which baud rate generator the device 28*0883c2c0SZhao Qiang is associated with. If absent, an unused BRG 29*0883c2c0SZhao Qiang should be dynamically allocated. If zero, the 30*0883c2c0SZhao Qiang device uses an external clock rather than a BRG. 31*0883c2c0SZhao Qiang 32*0883c2c0SZhao Qiang- reg : Unless otherwise specified, the first resource represents the 33*0883c2c0SZhao Qiang scc/fcc/ucc registers, and the second represents the device's 34*0883c2c0SZhao Qiang parameter RAM region (if it has one). 35*0883c2c0SZhao Qiang 36*0883c2c0SZhao Qiang* Multi-User RAM (MURAM) 37*0883c2c0SZhao Qiang 38*0883c2c0SZhao QiangThe multi-user/dual-ported RAM is expressed as a bus under the CPM node. 39*0883c2c0SZhao Qiang 40*0883c2c0SZhao QiangRanges must be set up subject to the following restrictions: 41*0883c2c0SZhao Qiang 42*0883c2c0SZhao Qiang- Children's reg nodes must be offsets from the start of all muram, even 43*0883c2c0SZhao Qiang if the user-data area does not begin at zero. 44*0883c2c0SZhao Qiang- If multiple range entries are used, the difference between the parent 45*0883c2c0SZhao Qiang address and the child address must be the same in all, so that a single 46*0883c2c0SZhao Qiang mapping can cover them all while maintaining the ability to determine 47*0883c2c0SZhao Qiang CPM-side offsets with pointer subtraction. It is recommended that 48*0883c2c0SZhao Qiang multiple range entries not be used. 49*0883c2c0SZhao Qiang- A child address of zero must be translatable, even if no reg resources 50*0883c2c0SZhao Qiang contain it. 51*0883c2c0SZhao Qiang 52*0883c2c0SZhao QiangA child "data" node must exist, compatible with "fsl,cpm-muram-data", to 53*0883c2c0SZhao Qiangindicate the portion of muram that is usable by the OS for arbitrary 54*0883c2c0SZhao Qiangpurposes. The data node may have an arbitrary number of reg resources, 55*0883c2c0SZhao Qiangall of which contribute to the allocatable muram pool. 56*0883c2c0SZhao Qiang 57*0883c2c0SZhao QiangExample, based on mpc8272: 58*0883c2c0SZhao Qiang muram@0 { 59*0883c2c0SZhao Qiang #address-cells = <1>; 60*0883c2c0SZhao Qiang #size-cells = <1>; 61*0883c2c0SZhao Qiang ranges = <0 0 10000>; 62*0883c2c0SZhao Qiang 63*0883c2c0SZhao Qiang data@0 { 64*0883c2c0SZhao Qiang compatible = "fsl,cpm-muram-data"; 65*0883c2c0SZhao Qiang reg = <0 2000 9800 800>; 66*0883c2c0SZhao Qiang }; 67*0883c2c0SZhao Qiang }; 68