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Searched refs:virt_memmap (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/hw/mips/
H A Dloongson3_virt.c69 const MemMapEntry virt_memmap[] = { variable
287 hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base; in fw_conf_init()
439 ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size); in loongson3_virt_devices_init()
441 virt_memmap[VIRT_PCIE_ECAM].base, in loongson3_virt_devices_init()
447 mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base, in loongson3_virt_devices_init()
448 virt_memmap[VIRT_PCIE_MMIO].size); in loongson3_virt_devices_init()
450 virt_memmap[VIRT_PCIE_MMIO].base, in loongson3_virt_devices_init()
456 virt_memmap[VIRT_PCIE_PIO].size); in loongson3_virt_devices_init()
458 virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias); in loongson3_virt_devices_init()
459 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base); in loongson3_virt_devices_init()
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H A Dloongson3_bootp.c74 s->uarts[0].uart_base = cpu_to_le64(virt_memmap[VIRT_UART].base); in init_system_loongson()
84 irq_info->pci_mem_start_addr = cpu_to_le64(virt_memmap[VIRT_PCIE_MMIO].base); in init_irq_source()
85 irq_info->pci_mem_end_addr = cpu_to_le64(virt_memmap[VIRT_PCIE_MMIO].base + in init_irq_source()
86 virt_memmap[VIRT_PCIE_MMIO].size - 1); in init_irq_source()
87 irq_info->pci_io_start_addr = cpu_to_le64(virt_memmap[VIRT_PCIE_PIO].base); in init_irq_source()
H A Dloongson3_bootp.h234 extern const MemMapEntry virt_memmap[];
/openbmc/qemu/hw/openrisc/
H A Dvirt.c75 } virt_memmap[] = { variable
499 openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size, in openrisc_virt_init()
503 openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base, in openrisc_virt_init()
504 virt_memmap[VIRT_OMPIC].size, in openrisc_virt_init()
508 openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base, in openrisc_virt_init()
509 virt_memmap[VIRT_UART].size, in openrisc_virt_init()
512 openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base, in openrisc_virt_init()
513 virt_memmap[VIRT_TEST].size); in openrisc_virt_init()
515 openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base, in openrisc_virt_init()
516 virt_memmap[VIRT_RTC].size, smp_cpus, cpus, in openrisc_virt_init()
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/openbmc/qemu/hw/riscv/
H A Dvirt.c71 static const MemMapEntry virt_memmap[] = { variable
157 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; in virt_flash_map()
158 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; in virt_flash_map()
981 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; in create_fdt_flash()
982 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; in create_fdt_flash()
1017 (long) virt_memmap[VIRT_PCIE_ECAM].base); in create_fdt_virtio_iommu()
1045 (long) virt_memmap[VIRT_PCIE_ECAM].base); in create_fdt_iommu()
1065 create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, in finalize_fdt()
1069 create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); in finalize_fdt()
1071 create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); in finalize_fdt()
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