xref: /openbmc/qemu/hw/mips/loongson3_bootp.h (revision 80748eb4fbc70f0a3ae423f2c01cb5a4584d803f)
1d2245e2dSHuacai Chen /*
2d2245e2dSHuacai Chen  * LEFI (a UEFI-like interface for BIOS-Kernel boot parameters) data structures
3d2245e2dSHuacai Chen  * defined at arch/mips/include/asm/mach-loongson64/boot_param.h in Linux kernel
4d2245e2dSHuacai Chen  *
5d2245e2dSHuacai Chen  * Copyright (c) 2017-2020 Huacai Chen (chenhc@lemote.com)
6d2245e2dSHuacai Chen  * Copyright (c) 2017-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
7d2245e2dSHuacai Chen  *
8d2245e2dSHuacai Chen  * This program is free software: you can redistribute it and/or modify
9d2245e2dSHuacai Chen  * it under the terms of the GNU General Public License as published by
10d2245e2dSHuacai Chen  * the Free Software Foundation, either version 2 of the License, or
11d2245e2dSHuacai Chen  * (at your option) any later version.
12d2245e2dSHuacai Chen  *
13d2245e2dSHuacai Chen  * This program is distributed in the hope that it will be useful,
14d2245e2dSHuacai Chen  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15d2245e2dSHuacai Chen  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16d2245e2dSHuacai Chen  * GNU General Public License for more details.
17d2245e2dSHuacai Chen  *
18d2245e2dSHuacai Chen  * You should have received a copy of the GNU General Public License
19d2245e2dSHuacai Chen  * along with this program. If not, see <https://www.gnu.org/licenses/>.
20d2245e2dSHuacai Chen  */
21d2245e2dSHuacai Chen 
22d2245e2dSHuacai Chen #ifndef HW_MIPS_LOONGSON3_BOOTP_H
23d2245e2dSHuacai Chen #define HW_MIPS_LOONGSON3_BOOTP_H
24d2245e2dSHuacai Chen 
25d2245e2dSHuacai Chen struct efi_memory_map_loongson {
26d2245e2dSHuacai Chen     uint16_t vers;               /* version of efi_memory_map */
27d2245e2dSHuacai Chen     uint32_t nr_map;             /* number of memory_maps */
28a1b93551SManos Pitsidianakis     uint32_t mem_freq;           /* memory frequency */
29d2245e2dSHuacai Chen     struct mem_map {
30d2245e2dSHuacai Chen         uint32_t node_id;        /* node_id which memory attached to */
31d2245e2dSHuacai Chen         uint32_t mem_type;       /* system memory, pci memory, pci io, etc. */
32d2245e2dSHuacai Chen         uint64_t mem_start;      /* memory map start address */
33d2245e2dSHuacai Chen         uint32_t mem_size;       /* each memory_map size, not the total size */
34d2245e2dSHuacai Chen     } map[128];
35d2245e2dSHuacai Chen } QEMU_PACKED;
36d2245e2dSHuacai Chen 
37d2245e2dSHuacai Chen enum loongson_cpu_type {
38d2245e2dSHuacai Chen     Legacy_2E = 0x0,
39d2245e2dSHuacai Chen     Legacy_2F = 0x1,
40d2245e2dSHuacai Chen     Legacy_3A = 0x2,
41d2245e2dSHuacai Chen     Legacy_3B = 0x3,
42d2245e2dSHuacai Chen     Legacy_1A = 0x4,
43d2245e2dSHuacai Chen     Legacy_1B = 0x5,
44d2245e2dSHuacai Chen     Legacy_2G = 0x6,
45d2245e2dSHuacai Chen     Legacy_2H = 0x7,
46d2245e2dSHuacai Chen     Loongson_1A = 0x100,
47d2245e2dSHuacai Chen     Loongson_1B = 0x101,
48d2245e2dSHuacai Chen     Loongson_2E = 0x200,
49d2245e2dSHuacai Chen     Loongson_2F = 0x201,
50d2245e2dSHuacai Chen     Loongson_2G = 0x202,
51d2245e2dSHuacai Chen     Loongson_2H = 0x203,
52d2245e2dSHuacai Chen     Loongson_3A = 0x300,
53d2245e2dSHuacai Chen     Loongson_3B = 0x301
54d2245e2dSHuacai Chen };
55d2245e2dSHuacai Chen 
56d2245e2dSHuacai Chen /*
57d2245e2dSHuacai Chen  * Capability and feature descriptor structure for MIPS CPU
58d2245e2dSHuacai Chen  */
59d2245e2dSHuacai Chen struct efi_cpuinfo_loongson {
60d2245e2dSHuacai Chen     uint16_t vers;               /* version of efi_cpuinfo_loongson */
61d2245e2dSHuacai Chen     uint32_t processor_id;       /* PRID, e.g. 6305, 6306 */
62d2245e2dSHuacai Chen     uint32_t cputype;            /* Loongson_3A/3B, etc. */
63d2245e2dSHuacai Chen     uint32_t total_node;         /* num of total numa nodes */
64d2245e2dSHuacai Chen     uint16_t cpu_startup_core_id;   /* Boot core id */
65d2245e2dSHuacai Chen     uint16_t reserved_cores_mask;
66d2245e2dSHuacai Chen     uint32_t cpu_clock_freq;     /* cpu_clock */
67d2245e2dSHuacai Chen     uint32_t nr_cpus;
68d2245e2dSHuacai Chen     char cpuname[64];
69d2245e2dSHuacai Chen } QEMU_PACKED;
70d2245e2dSHuacai Chen 
71d2245e2dSHuacai Chen #define MAX_UARTS 64
72d2245e2dSHuacai Chen struct uart_device {
73d2245e2dSHuacai Chen     uint32_t iotype;
74d2245e2dSHuacai Chen     uint32_t uartclk;
75d2245e2dSHuacai Chen     uint32_t int_offset;
76d2245e2dSHuacai Chen     uint64_t uart_base;
77d2245e2dSHuacai Chen } QEMU_PACKED;
78d2245e2dSHuacai Chen 
79d2245e2dSHuacai Chen #define MAX_SENSORS 64
80d2245e2dSHuacai Chen #define SENSOR_TEMPER  0x00000001
81d2245e2dSHuacai Chen #define SENSOR_VOLTAGE 0x00000002
82d2245e2dSHuacai Chen #define SENSOR_FAN     0x00000004
83d2245e2dSHuacai Chen struct sensor_device {
84d2245e2dSHuacai Chen     char name[32];  /* a formal name */
85d2245e2dSHuacai Chen     char label[64]; /* a flexible description */
86d2245e2dSHuacai Chen     uint32_t type;       /* SENSOR_* */
87d2245e2dSHuacai Chen     uint32_t id;         /* instance id of a sensor-class */
88d2245e2dSHuacai Chen     uint32_t fan_policy; /* step speed or constant speed */
89d2245e2dSHuacai Chen     uint32_t fan_percent;/* only for constant speed policy */
90d2245e2dSHuacai Chen     uint64_t base_addr;  /* base address of device registers */
91d2245e2dSHuacai Chen } QEMU_PACKED;
92d2245e2dSHuacai Chen 
93d2245e2dSHuacai Chen struct system_loongson {
94d2245e2dSHuacai Chen     uint16_t vers;               /* version of system_loongson */
95d2245e2dSHuacai Chen     uint32_t ccnuma_smp;         /* 0: no numa; 1: has numa */
96d2245e2dSHuacai Chen     uint32_t sing_double_channel;/* 1: single; 2: double */
97d2245e2dSHuacai Chen     uint32_t nr_uarts;
98d2245e2dSHuacai Chen     struct uart_device uarts[MAX_UARTS];
99d2245e2dSHuacai Chen     uint32_t nr_sensors;
100d2245e2dSHuacai Chen     struct sensor_device sensors[MAX_SENSORS];
101d2245e2dSHuacai Chen     char has_ec;
102d2245e2dSHuacai Chen     char ec_name[32];
103d2245e2dSHuacai Chen     uint64_t ec_base_addr;
104d2245e2dSHuacai Chen     char has_tcm;
105d2245e2dSHuacai Chen     char tcm_name[32];
106d2245e2dSHuacai Chen     uint64_t tcm_base_addr;
107d2245e2dSHuacai Chen     uint64_t workarounds;
108d2245e2dSHuacai Chen     uint64_t of_dtb_addr; /* NULL if not support */
109d2245e2dSHuacai Chen } QEMU_PACKED;
110d2245e2dSHuacai Chen 
111d2245e2dSHuacai Chen struct irq_source_routing_table {
112d2245e2dSHuacai Chen     uint16_t vers;
113d2245e2dSHuacai Chen     uint16_t size;
114d2245e2dSHuacai Chen     uint16_t rtr_bus;
115d2245e2dSHuacai Chen     uint16_t rtr_devfn;
116d2245e2dSHuacai Chen     uint32_t vendor;
117d2245e2dSHuacai Chen     uint32_t device;
118d2245e2dSHuacai Chen     uint32_t PIC_type;           /* conform use HT or PCI to route to CPU-PIC */
119d2245e2dSHuacai Chen     uint64_t ht_int_bit;         /* 3A: 1<<24; 3B: 1<<16 */
120d2245e2dSHuacai Chen     uint64_t ht_enable;          /* irqs used in this PIC */
121d2245e2dSHuacai Chen     uint32_t node_id;            /* node id: 0x0-0; 0x1-1; 0x10-2; 0x11-3 */
122d2245e2dSHuacai Chen     uint64_t pci_mem_start_addr;
123d2245e2dSHuacai Chen     uint64_t pci_mem_end_addr;
124d2245e2dSHuacai Chen     uint64_t pci_io_start_addr;
125d2245e2dSHuacai Chen     uint64_t pci_io_end_addr;
126d2245e2dSHuacai Chen     uint64_t pci_config_addr;
127d2245e2dSHuacai Chen     uint16_t dma_mask_bits;
128d2245e2dSHuacai Chen     uint16_t dma_noncoherent;
129d2245e2dSHuacai Chen } QEMU_PACKED;
130d2245e2dSHuacai Chen 
131d2245e2dSHuacai Chen struct interface_info {
132d2245e2dSHuacai Chen     uint16_t vers;               /* version of the specificition */
133d2245e2dSHuacai Chen     uint16_t size;
134d2245e2dSHuacai Chen     uint8_t  flag;
135d2245e2dSHuacai Chen     char description[64];
136d2245e2dSHuacai Chen } QEMU_PACKED;
137d2245e2dSHuacai Chen 
138d2245e2dSHuacai Chen #define MAX_RESOURCE_NUMBER 128
139d2245e2dSHuacai Chen struct resource_loongson {
140d2245e2dSHuacai Chen     uint64_t start;              /* resource start address */
141d2245e2dSHuacai Chen     uint64_t end;                /* resource end address */
142d2245e2dSHuacai Chen     char name[64];
143d2245e2dSHuacai Chen     uint32_t flags;
144d2245e2dSHuacai Chen };
145d2245e2dSHuacai Chen 
146d2245e2dSHuacai Chen struct archdev_data {};          /* arch specific additions */
147d2245e2dSHuacai Chen 
148d2245e2dSHuacai Chen struct board_devices {
149d2245e2dSHuacai Chen     char name[64];               /* hold the device name */
150d2245e2dSHuacai Chen     uint32_t num_resources;      /* number of device_resource */
151d2245e2dSHuacai Chen     /* for each device's resource */
152d2245e2dSHuacai Chen     struct resource_loongson resource[MAX_RESOURCE_NUMBER];
153d2245e2dSHuacai Chen     /* arch specific additions */
154d2245e2dSHuacai Chen     struct archdev_data archdata;
155d2245e2dSHuacai Chen };
156d2245e2dSHuacai Chen 
157d2245e2dSHuacai Chen struct loongson_special_attribute {
158d2245e2dSHuacai Chen     uint16_t vers;               /* version of this special */
159a1b93551SManos Pitsidianakis     char special_name[64];       /* special_attribute_name */
160d2245e2dSHuacai Chen     uint32_t loongson_special_type; /* type of special device */
161d2245e2dSHuacai Chen     /* for each device's resource */
162d2245e2dSHuacai Chen     struct resource_loongson resource[MAX_RESOURCE_NUMBER];
163d2245e2dSHuacai Chen };
164d2245e2dSHuacai Chen 
165d2245e2dSHuacai Chen struct loongson_params {
166d2245e2dSHuacai Chen     uint64_t memory_offset;      /* efi_memory_map_loongson struct offset */
167d2245e2dSHuacai Chen     uint64_t cpu_offset;         /* efi_cpuinfo_loongson struct offset */
168d2245e2dSHuacai Chen     uint64_t system_offset;      /* system_loongson struct offset */
169d2245e2dSHuacai Chen     uint64_t irq_offset;         /* irq_source_routing_table struct offset */
170d2245e2dSHuacai Chen     uint64_t interface_offset;   /* interface_info struct offset */
171d2245e2dSHuacai Chen     uint64_t special_offset;     /* loongson_special_attribute struct offset */
172d2245e2dSHuacai Chen     uint64_t boarddev_table_offset;  /* board_devices offset */
173d2245e2dSHuacai Chen };
174d2245e2dSHuacai Chen 
175d2245e2dSHuacai Chen struct smbios_tables {
176d2245e2dSHuacai Chen     uint16_t vers;               /* version of smbios */
177d2245e2dSHuacai Chen     uint64_t vga_bios;           /* vga_bios address */
178d2245e2dSHuacai Chen     struct loongson_params lp;
179d2245e2dSHuacai Chen };
180d2245e2dSHuacai Chen 
181d2245e2dSHuacai Chen struct efi_reset_system_t {
182d2245e2dSHuacai Chen     uint64_t ResetCold;
183d2245e2dSHuacai Chen     uint64_t ResetWarm;
184d2245e2dSHuacai Chen     uint64_t ResetType;
185d2245e2dSHuacai Chen     uint64_t Shutdown;
186d2245e2dSHuacai Chen     uint64_t DoSuspend; /* NULL if not support */
187d2245e2dSHuacai Chen };
188d2245e2dSHuacai Chen 
189d2245e2dSHuacai Chen struct efi_loongson {
190d2245e2dSHuacai Chen     uint64_t mps;                /* MPS table */
191d2245e2dSHuacai Chen     uint64_t acpi;               /* ACPI table (IA64 ext 0.71) */
192d2245e2dSHuacai Chen     uint64_t acpi20;             /* ACPI table (ACPI 2.0) */
193d2245e2dSHuacai Chen     struct smbios_tables smbios; /* SM BIOS table */
194d2245e2dSHuacai Chen     uint64_t sal_systab;         /* SAL system table */
195d2245e2dSHuacai Chen     uint64_t boot_info;          /* boot info table */
196d2245e2dSHuacai Chen };
197d2245e2dSHuacai Chen 
198d2245e2dSHuacai Chen struct boot_params {
199d2245e2dSHuacai Chen     struct efi_loongson efi;
200d2245e2dSHuacai Chen     struct efi_reset_system_t reset_system;
201d2245e2dSHuacai Chen };
202d2245e2dSHuacai Chen 
203*c3425158SJiaxun Yang #define LOONGSON3_CORE_PER_NODE 4
204*c3425158SJiaxun Yang 
205d2245e2dSHuacai Chen /* Overall MMIO & Memory layout */
206d2245e2dSHuacai Chen enum {
207d2245e2dSHuacai Chen     VIRT_LOWMEM,
208d2245e2dSHuacai Chen     VIRT_PM,
209d2245e2dSHuacai Chen     VIRT_FW_CFG,
210d2245e2dSHuacai Chen     VIRT_RTC,
211d2245e2dSHuacai Chen     VIRT_PCIE_PIO,
212d2245e2dSHuacai Chen     VIRT_PCIE_ECAM,
213d2245e2dSHuacai Chen     VIRT_BIOS_ROM,
214d2245e2dSHuacai Chen     VIRT_UART,
215d2245e2dSHuacai Chen     VIRT_LIOINTC,
216*c3425158SJiaxun Yang     VIRT_IPI,
217d2245e2dSHuacai Chen     VIRT_PCIE_MMIO,
218d2245e2dSHuacai Chen     VIRT_HIGHMEM
219d2245e2dSHuacai Chen };
220d2245e2dSHuacai Chen 
221d2245e2dSHuacai Chen /* Low MEM layout for QEMU kernel loader */
222d2245e2dSHuacai Chen enum {
223d2245e2dSHuacai Chen     LOADER_KERNEL,
224d2245e2dSHuacai Chen     LOADER_INITRD,
225d2245e2dSHuacai Chen     LOADER_CMDLINE
226d2245e2dSHuacai Chen };
227d2245e2dSHuacai Chen 
228d2245e2dSHuacai Chen /* BIOS ROM layout for QEMU kernel loader */
229d2245e2dSHuacai Chen enum {
230d2245e2dSHuacai Chen     LOADER_BOOTROM,
231d2245e2dSHuacai Chen     LOADER_PARAM,
232d2245e2dSHuacai Chen };
233d2245e2dSHuacai Chen 
234ac9b0117SBin Meng extern const MemMapEntry virt_memmap[];
235d2245e2dSHuacai Chen void init_loongson_params(struct loongson_params *lp, void *p,
236d2245e2dSHuacai Chen                           uint64_t cpu_freq, uint64_t ram_size);
237d2245e2dSHuacai Chen void init_reset_system(struct efi_reset_system_t *reset);
238d2245e2dSHuacai Chen 
239d2245e2dSHuacai Chen #endif
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