| /openbmc/linux/drivers/accel/habanalabs/include/gaudi2/ |
| H A D | gaudi2_async_ids_map_extended.h | 27 int reset; member
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | zynq-reset.txt | 8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
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| H A D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
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| H A D | ti-syscon-reset.txt | 4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
13 and provides reset management functionality for various hardware modules
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
31 Should contain 7 cells for each reset exposed to
33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
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| H A D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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| H A D | img,pistachio-reset.txt | 4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
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| /openbmc/linux/drivers/reset/ |
| H A D | Makefile | 7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
11 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
12 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
13 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
14 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
15 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
16 obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
[all …]
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| H A D | reset-sunplus.c | 115 struct sp_reset *reset = to_sp_reset(rcdev); in sp_reset_update() local
121 writel(val, reset->base + (index * 4)); in sp_reset_update()
141 struct sp_reset *reset = to_sp_reset(rcdev); in sp_reset_status() local
146 reg = readl(reset->base + (index * 4)); in sp_reset_status()
160 struct sp_reset *reset = container_of(nb, struct sp_reset, notifier); in sp_restart() local
162 sp_reset_assert(&reset->rcdev, 0); in sp_restart()
163 sp_reset_deassert(&reset->rcdev, 0); in sp_restart()
171 struct sp_reset *reset; in sp_reset_probe() local
175 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in sp_reset_probe()
176 if (!reset) in sp_reset_probe()
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| H A D | Kconfig | 11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
22 This option enables support for the external reset functions for
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
43 This enables the reset controller driver for BCM6345 SoCs.
50 This enables the reset controller driver for Marvell Berlin SoCs.
53 tristate "Broadcom STB reset controller"
57 This enables the reset controller driver for Broadcom STB SoCs using
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| /openbmc/linux/drivers/power/reset/ |
| H A D | at91-reset.c | 118 struct at91_reset *reset = container_of(this, struct at91_reset, nb); in at91_reset() local
141 : "r" (reset->ramc_base[0]), in at91_reset()
142 "r" (reset->ramc_base[1]), in at91_reset()
143 "r" (reset->rstc_base), in at91_reset()
146 "r" (reset->data->reset_args), in at91_reset()
147 "r" (reset->ramc_lpr) in at91_reset()
153 static const char *at91_reset_reason(struct at91_reset *reset) in at91_reset_reason() argument
155 u32 reg = readl(reset->rstc_base + AT91_RSTC_SR); in at91_reset_reason()
195 struct at91_reset *reset = platform_get_drvdata(pdev); in power_on_reason_show() local
197 return sprintf(buf, "%s\n", at91_reset_reason(reset)); in power_on_reason_show()
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | reset.rst | 10 Reset controllers are central units that control the reset signals to multiple
12 The reset controller API is split into two parts:
14 <#reset-consumer-api>`__), which allows peripheral drivers to request control
15 over their reset input signals, and the `reset controller driver interface
16 <#reset-controller-driver-interface>`__ (`API reference
17 <#reset-controller-driver-api>`__), which is used by drivers for reset
18 controller devices to register their reset controls to provide them to the
21 While some reset controller hardware units also implement system restart
22 functionality, restart handlers are out of scope for the reset controller API.
27 The reset controller API uses these terms with a specific meaning:
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| /openbmc/linux/drivers/clk/visconti/ |
| H A D | reset.c | 25 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_assert() local
26 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_assert()
31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert()
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst); in visconti_reset_assert()
33 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_assert()
40 struct visconti_reset *reset = to_visconti_reset(rcdev); in visconti_reset_deassert() local
41 const struct visconti_reset_data *data = &reset->resets[id]; in visconti_reset_deassert()
46 spin_lock_irqsave(reset->lock, flags); in visconti_reset_deassert()
47 ret = regmap_update_bits(reset->regmap, data->rsoff_offset, rst, rst); in visconti_reset_deassert()
48 spin_unlock_irqrestore(reset->lock, flags); in visconti_reset_deassert()
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| /openbmc/u-boot/doc/device-tree-bindings/reset/ |
| H A D | reset.txt | 3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
[all …]
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| /openbmc/qemu/hw/misc/ |
| H A D | xlnx-versal-crl.c | 154 .reset = 0x1,
162 .reset = 0x1,
165 .reset = 0x24809,
168 .reset = 0x2000000,
173 .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
178 .reset = 0x2000100,
181 .reset = 0x6000300,
184 .reset = 0x2000800,
187 .reset = 0xe000300,
190 .reset = 0x2000500,
[all …]
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| H A D | xlnx-zynqmp-crf.c | 84 .reset = 0x1,
92 .reset = 0x12c09,
99 .reset = 0x2c09,
106 .reset = 0x12809,
113 .reset = 0x3f,
117 .reset = 0x400,
120 .reset = 0x400,
123 .reset = 0x400,
126 .reset = 0x3000400,
129 .reset = 0x2500,
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| /openbmc/qemu/tests/qtest/ |
| H A D | stm32l4x5_gpio-test.c | 159 static uint32_t reset(uint32_t gpio, unsigned int offset) in reset() function
226 g_assert_cmphex(moder, ==, reset(GPIO_A, MODER)); in test_idr_reset_value()
227 g_assert_cmphex(odr, ==, reset(GPIO_A, ODR)); in test_idr_reset_value()
228 g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER)); in test_idr_reset_value()
230 g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR)); in test_idr_reset_value()
232 g_assert_cmphex(idr, ==, reset(GPIO_A, IDR)); in test_idr_reset_value()
241 g_assert_cmphex(moder, ==, reset(GPIO_B, MODER)); in test_idr_reset_value()
242 g_assert_cmphex(odr, ==, reset(GPIO_B, ODR)); in test_idr_reset_value()
243 g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER)); in test_idr_reset_value()
245 g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR)); in test_idr_reset_value()
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| /openbmc/u-boot/drivers/reset/ |
| H A D | Makefile | 6 obj-$(CONFIG_DM_RESET) += reset-uclass.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
8 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
9 obj-$(CONFIG_STI_RESET) += sti-reset.o
10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
11 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
12 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
13 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
14 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
15 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
[all …]
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| H A D | Kconfig | 4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable the sandbox reset test driver"
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
24 bool "Enable the STi reset"
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| /openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
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| /openbmc/linux/arch/arm64/boot/dts/apple/ |
| H A D | t8103-pmgr.dtsi | 14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
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| H A D | t8112-pmgr.dtsi | 14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
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| H A D | t600x-pmgr.dtsi | 13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
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| /openbmc/linux/drivers/pmdomain/ti/ |
| H A D | omap_prm.c | 724 static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) in _is_valid_reset() argument
726 if (reset->mask & BIT(id)) in _is_valid_reset()
732 static int omap_reset_get_st_bit(struct omap_reset_data *reset, in omap_reset_get_st_bit() argument
735 const struct omap_rst_map *map = reset->prm->data->rstmap; in omap_reset_get_st_bit()
750 struct omap_reset_data *reset = to_omap_reset_data(rcdev); in omap_reset_status() local
752 int st_bit = omap_reset_get_st_bit(reset, id); in omap_reset_status()
753 bool has_rstst = reset->prm->data->rstst || in omap_reset_status()
754 (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); in omap_reset_status()
761 v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); in omap_reset_status()
769 v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); in omap_reset_status()
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| /openbmc/u-boot/drivers/sysreset/ |
| H A D | Kconfig | 2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
12 board. Each driver can provide a reset method which will be called
13 to effect a reset. The uclass will try all available drivers when
19 bool "Enable support for GPIO reset driver"
22 Reset support via GPIO pin connected reset logic. This is used for
23 example on Microblaze where reset logic can be controlled via GPIO
24 pin which triggers cpu reset.
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| /openbmc/qemu/docs/devel/ |
| H A D | reset.rst | 6 The reset of qemu objects is handled using the resettable interface declared
10 whole group can be reset consistently. Each individual member object does not
12 reset first) are addressed.
17 Triggering reset
24 You can apply a reset to an object using ``resettable_assert_reset()``. You need
25 to call ``resettable_release_reset()`` to release the object from reset. To
26 instantly reset an object, without keeping it in reset state, just call
28 object to reset and a reset type.
30 The Resettable interface handles reset types with an enum ``ResetType``:
33 Cold reset is supported by every resettable object. In QEMU, it means we reset
[all …]
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