1caee0055SIvan Khoronzhuk* Device tree bindings for Texas Instruments keystone reset 2caee0055SIvan Khoronzhuk 3caee0055SIvan KhoronzhukThis node is intended to allow SoC reset in case of software reset 4caee0055SIvan Khoronzhukof selected watchdogs. 5caee0055SIvan Khoronzhuk 6caee0055SIvan KhoronzhukThe Keystone SoCs can contain up to 4 watchdog timers to reset 7caee0055SIvan KhoronzhukSoC. Each watchdog timer event input is connected to the Reset Mux 8caee0055SIvan Khoronzhukblock. The Reset Mux block can be configured to cause reset or not. 9caee0055SIvan Khoronzhuk 10caee0055SIvan KhoronzhukAdditionally soft or hard reset can be configured. 11caee0055SIvan Khoronzhuk 12caee0055SIvan KhoronzhukRequired properties: 13caee0055SIvan Khoronzhuk 14caee0055SIvan Khoronzhuk- compatible: ti,keystone-reset 15caee0055SIvan Khoronzhuk 16caee0055SIvan Khoronzhuk- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to 17caee0055SIvan Khoronzhuk access pll controller registers and the offset to use 18caee0055SIvan Khoronzhuk reset control registers. 19caee0055SIvan Khoronzhuk 20caee0055SIvan Khoronzhuk- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to 21caee0055SIvan Khoronzhuk access device state control registers and the offset 22caee0055SIvan Khoronzhuk in order to use mux block registers for all watchdogs. 23caee0055SIvan Khoronzhuk 24caee0055SIvan KhoronzhukOptional properties: 25caee0055SIvan Khoronzhuk 26caee0055SIvan Khoronzhuk- ti,soft-reset: Boolean option indicating soft reset. 27caee0055SIvan Khoronzhuk By default hard reset is used. 28caee0055SIvan Khoronzhuk 29caee0055SIvan Khoronzhuk- ti,wdt-list: WDT list that can cause SoC reset. It's not related 30caee0055SIvan Khoronzhuk to WDT driver, it's just needed to enable a SoC related 31caee0055SIvan Khoronzhuk reset that's triggered by one of WDTs. The list is 32caee0055SIvan Khoronzhuk in format: <0>, <2>; It can be in random order and 33caee0055SIvan Khoronzhuk begins from 0 to 3, as keystone can contain up to 4 SoC 34caee0055SIvan Khoronzhuk reset watchdogs and can be in random order. 35caee0055SIvan Khoronzhuk 36caee0055SIvan KhoronzhukExample 1: 37caee0055SIvan KhoronzhukSetup keystone reset so that in case software reset or 38caee0055SIvan KhoronzhukWDT0 is triggered it issues hard reset for SoC. 39caee0055SIvan Khoronzhuk 40*48c926cdSMarco Franchipllctrl: pll-controller@2310000 { 41caee0055SIvan Khoronzhuk compatible = "ti,keystone-pllctrl", "syscon"; 42caee0055SIvan Khoronzhuk reg = <0x02310000 0x200>; 43caee0055SIvan Khoronzhuk}; 44caee0055SIvan Khoronzhuk 45*48c926cdSMarco Franchidevctrl: device-state-control@2620000 { 46caee0055SIvan Khoronzhuk compatible = "ti,keystone-devctrl", "syscon"; 47caee0055SIvan Khoronzhuk reg = <0x02620000 0x1000>; 48caee0055SIvan Khoronzhuk}; 49caee0055SIvan Khoronzhuk 50caee0055SIvan Khoronzhukrstctrl: reset-controller { 51caee0055SIvan Khoronzhuk compatible = "ti,keystone-reset"; 52caee0055SIvan Khoronzhuk ti,syscon-pll = <&pllctrl 0xe4>; 53caee0055SIvan Khoronzhuk ti,syscon-dev = <&devctrl 0x328>; 54caee0055SIvan Khoronzhuk ti,wdt-list = <0>; 55caee0055SIvan Khoronzhuk}; 56caee0055SIvan Khoronzhuk 57caee0055SIvan KhoronzhukExample 2: 58caee0055SIvan KhoronzhukSetup keystone reset so that in case of software reset or 59caee0055SIvan KhoronzhukWDT0 or WDT2 is triggered it issues soft reset for SoC. 60caee0055SIvan Khoronzhuk 61caee0055SIvan Khoronzhukrstctrl: reset-controller { 62caee0055SIvan Khoronzhuk compatible = "ti,keystone-reset"; 63caee0055SIvan Khoronzhuk ti,syscon-pll = <&pllctrl 0xe4>; 64caee0055SIvan Khoronzhuk ti,syscon-dev = <&devctrl 0x328>; 65caee0055SIvan Khoronzhuk ti,wdt-list = <0>, <2>; 66caee0055SIvan Khoronzhuk ti,soft-reset; 67caee0055SIvan Khoronzhuk}; 68