1*575c215cSMoritz FischerXilinx Zynq Reset Manager 2*575c215cSMoritz Fischer 3*575c215cSMoritz FischerThe Zynq AP-SoC has several different resets. 4*575c215cSMoritz Fischer 5*575c215cSMoritz FischerSee Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. 6*575c215cSMoritz Fischer 7*575c215cSMoritz FischerRequired properties: 8*575c215cSMoritz Fischer- compatible: "xlnx,zynq-reset" 9*575c215cSMoritz Fischer- reg: SLCR offset and size taken via syscon <0x200 0x48> 10*575c215cSMoritz Fischer- syscon: <&slcr> 11*575c215cSMoritz Fischer This should be a phandle to the Zynq's SLCR registers. 12*575c215cSMoritz Fischer- #reset-cells: Must be 1 13*575c215cSMoritz Fischer 14*575c215cSMoritz FischerThe Zynq Reset Manager needs to be a childnode of the SLCR. 15*575c215cSMoritz Fischer 16*575c215cSMoritz FischerExample: 17*575c215cSMoritz Fischer rstc: rstc@200 { 18*575c215cSMoritz Fischer compatible = "xlnx,zynq-reset"; 19*575c215cSMoritz Fischer reg = <0x200 0x48>; 20*575c215cSMoritz Fischer #reset-cells = <1>; 21*575c215cSMoritz Fischer syscon = <&slcr>; 22*575c215cSMoritz Fischer }; 23*575c215cSMoritz Fischer 24*575c215cSMoritz FischerReset outputs: 25*575c215cSMoritz Fischer 0 : soft reset 26*575c215cSMoritz Fischer 32 : ddr reset 27*575c215cSMoritz Fischer 64 : topsw reset 28*575c215cSMoritz Fischer 96 : dmac reset 29*575c215cSMoritz Fischer 128: usb0 reset 30*575c215cSMoritz Fischer 129: usb1 reset 31*575c215cSMoritz Fischer 160: gem0 reset 32*575c215cSMoritz Fischer 161: gem1 reset 33*575c215cSMoritz Fischer 164: gem0 rx reset 34*575c215cSMoritz Fischer 165: gem1 rx reset 35*575c215cSMoritz Fischer 166: gem0 ref reset 36*575c215cSMoritz Fischer 167: gem1 ref reset 37*575c215cSMoritz Fischer 192: sdio0 reset 38*575c215cSMoritz Fischer 193: sdio1 reset 39*575c215cSMoritz Fischer 196: sdio0 ref reset 40*575c215cSMoritz Fischer 197: sdio1 ref reset 41*575c215cSMoritz Fischer 224: spi0 reset 42*575c215cSMoritz Fischer 225: spi1 reset 43*575c215cSMoritz Fischer 226: spi0 ref reset 44*575c215cSMoritz Fischer 227: spi1 ref reset 45*575c215cSMoritz Fischer 256: can0 reset 46*575c215cSMoritz Fischer 257: can1 reset 47*575c215cSMoritz Fischer 258: can0 ref reset 48*575c215cSMoritz Fischer 259: can1 ref reset 49*575c215cSMoritz Fischer 288: i2c0 reset 50*575c215cSMoritz Fischer 289: i2c1 reset 51*575c215cSMoritz Fischer 320: uart0 reset 52*575c215cSMoritz Fischer 321: uart1 reset 53*575c215cSMoritz Fischer 322: uart0 ref reset 54*575c215cSMoritz Fischer 323: uart1 ref reset 55*575c215cSMoritz Fischer 352: gpio reset 56*575c215cSMoritz Fischer 384: lqspi reset 57*575c215cSMoritz Fischer 385: qspi ref reset 58*575c215cSMoritz Fischer 416: smc reset 59*575c215cSMoritz Fischer 417: smc ref reset 60*575c215cSMoritz Fischer 448: ocm reset 61*575c215cSMoritz Fischer 512: fpga0 out reset 62*575c215cSMoritz Fischer 513: fpga1 out reset 63*575c215cSMoritz Fischer 514: fpga2 out reset 64*575c215cSMoritz Fischer 515: fpga3 out reset 65*575c215cSMoritz Fischer 544: a9 reset 0 66*575c215cSMoritz Fischer 545: a9 reset 1 67*575c215cSMoritz Fischer 552: peri reset 68*575c215cSMoritz Fischer 69