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Searched refs:rcc (Results 1 – 25 of 84) sorted by relevance

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/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c.dtsi141 clocks = <&rcc TIM2_K>;
162 clocks = <&rcc TIM3_K>;
183 clocks = <&rcc TIM4_K>;
204 clocks = <&rcc TIM5_K>;
225 clocks = <&rcc TIM6_K>;
241 clocks = <&rcc TIM7_K>;
257 clocks = <&rcc TIM12_K>;
278 clocks = <&rcc TIM13_K>;
299 clocks = <&rcc TIM14_K>;
320 clocks = <&rcc LPTIM1_K>;
[all …]
H A Dstm32f429.dtsi47 #include <dt-bindings/mfd/stm32f4-rcc.h>
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
H A Dstm32f746.dtsi51 #include <dt-bindings/mfd/stm32f7-rcc.h>
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
95 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
102 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
112 rcc: rcc@40023810 { label
115 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
[all …]
H A Dstm32h743.dtsi46 #include <dt-bindings/mfd/stm32h7-rcc.h>
70 rcc: rcc@58024400 { label
73 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
84 clocks = <&rcc USART1_CK>;
92 clocks = <&rcc USART2_CK>;
99 clocks = <&rcc TIM5_CK>;
110 clocks = <&rcc FMC_CK>;
129 clocks = <&rcc SDMMC1_CK>;
130 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
H A Dstm32mp15-ddr.dtsi16 clocks = <&rcc AXIDCG>,
17 <&rcc DDRC1>,
18 <&rcc DDRC2>,
19 <&rcc DDRPHYC>,
20 <&rcc DDRCAPB>,
21 <&rcc DDRPHYCAPB>;
H A Dstm32mp157-pinctrl.dtsi25 clocks = <&rcc GPIOA>;
37 clocks = <&rcc GPIOB>;
49 clocks = <&rcc GPIOC>;
61 clocks = <&rcc GPIOD>;
73 clocks = <&rcc GPIOE>;
85 clocks = <&rcc GPIOF>;
97 clocks = <&rcc GPIOG>;
109 clocks = <&rcc GPIOH>;
121 clocks = <&rcc GPIOI>;
133 clocks = <&rcc GPIOJ>;
[all …]
H A Dstm32h743-pinctrl.dtsi59 clocks = <&rcc GPIOA_CK>;
68 clocks = <&rcc GPIOB_CK>;
77 clocks = <&rcc GPIOC_CK>;
86 clocks = <&rcc GPIOD_CK>;
95 clocks = <&rcc GPIOE_CK>;
104 clocks = <&rcc GPIOF_CK>;
113 clocks = <&rcc GPIOG_CK>;
122 clocks = <&rcc GPIOH_CK>;
131 clocks = <&rcc GPIOI_CK>;
140 clocks = <&rcc GPIOJ_CK>;
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
H A Dstm32mp151.dtsi133 clocks = <&rcc TIM2_K>;
168 clocks = <&rcc TIM3_K>;
204 clocks = <&rcc TIM4_K>;
238 clocks = <&rcc TIM5_K>;
274 clocks = <&rcc TIM6_K>;
294 clocks = <&rcc TIM7_K>;
314 clocks = <&rcc TIM12_K>;
338 clocks = <&rcc TIM13_K>;
362 clocks = <&rcc TIM14_K>;
385 clocks = <&rcc LPTIM1_K>;
[all …]
H A Dstm32mp131.dtsi117 clocks = <&rcc TIM2_K>;
152 clocks = <&rcc TIM3_K>;
188 clocks = <&rcc TIM4_K>;
222 clocks = <&rcc TIM5_K>;
258 clocks = <&rcc TIM6_K>;
278 clocks = <&rcc TIM7_K>;
297 clocks = <&rcc LPTIM1_K>;
340 clocks = <&rcc SPI2_K>;
341 resets = <&rcc SPI2_R>;
365 clocks = <&rcc SPI3_K>;
[all …]
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32mp157c-ev1-scmi.dts39 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
61 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
65 &rcc {
66 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-ed1-scmi.dts38 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
71 &rcc {
72 compatible = "st,stm32mp1-rcc-secure", "syscon";
/openbmc/linux/drivers/clk/qcom/
H A Dclk-rpm.c257 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
261 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
263 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
267 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
270 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
278 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
282 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
284 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
288 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
291 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
23 rcc: rcc@40023800 {
26 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
46 - include/dt-bindings/mfd/stm32f4-rcc.h
52 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
57 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
74 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
94 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
H A Dst,stm32h7-rcc.txt11 "st,stm32h743-rcc"
33 rcc: rcc@58024400 {
36 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
127 clocks = <&rcc TIM5_CK>;
145 All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h
151 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dst,stm32-rcc.txt11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
53 - include/dt-bindings/mfd/stm32f4-rcc.h
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
[all …]
H A Dst,stm32h7-rcc.txt11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1171 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, in stm32mp1_ls_osc_set() argument
1174 u32 address = rcc + offset; in stm32mp1_ls_osc_set()
1182 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) in stm32mp1_hs_ocs_set() argument
1184 writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); in stm32mp1_hs_ocs_set()
1187 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, in stm32mp1_osc_wait() argument
1191 u32 address = rcc + offset; in stm32mp1_osc_wait()
1209 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, in stm32mp1_lse_enable() argument
1215 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1218 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1224 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) in stm32mp1_lse_enable()
[all …]
/openbmc/qemu/target/rx/
H A Dcpu.c76 RXCPUClass *rcc = RX_CPU_GET_CLASS(obj); in rx_cpu_reset_hold() local
80 if (rcc->parent_phases.hold) { in rx_cpu_reset_hold()
81 rcc->parent_phases.hold(obj, type); in rx_cpu_reset_hold()
124 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); in rx_cpu_realize() local
136 rcc->parent_realize(dev, errp); in rx_cpu_realize()
211 RXCPUClass *rcc = RX_CPU_CLASS(klass); in rx_cpu_class_init() local
215 &rcc->parent_realize); in rx_cpu_class_init()
217 &rcc->parent_phases); in rx_cpu_class_init()
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.c383 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
384 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
385 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
386 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
387 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
388 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
397 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
398 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
402 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
428 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
[all …]

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