xref: /openbmc/u-boot/arch/arm/dts/stm32f746.dtsi (revision 8ada17dde84954e36d8bc6ff62a6956686eb0ec4)

/*
 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
 *
 * Based on:
 * stm32f429.dtsi from Linux
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>

/ {
	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
};

	soc {
		u-boot,dm-pre-reloc;
		mac: ethernet@40028000 {
			compatible = "st,stm32-dwmac";
			reg = <0x40028000 0x8000>;
			reg-names = "stmmaceth";
			clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
				 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
			interrupts = <61>, <62>;
			interrupt-names = "macirq", "eth_wake_irq";
			snps,pbl = <8>;
			snps,mixed-burst;
			dma-ranges;
			status = "disabled";
		};

		fmc: fmc@A0000000 {
			compatible = "st,stm32-fmc";
			reg = <0xA0000000 0x1000>;
			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
			u-boot,dm-pre-reloc;
		};

		qspi: quadspi@A0001000 {
			compatible = "st,stm32-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
			reg-names = "qspi", "qspi_mm";
			interrupts = <92>;
			spi-max-frequency = <108000000>;
			clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
			resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
			status = "disabled";
		};
		usart1: serial@40011000 {
			compatible = "st,stm32f7-usart", "st,stm32f7-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
			status = "disabled";
			u-boot,dm-pre-reloc;
		};

		pwrcfg: power-config@58024800 {
			compatible = "syscon";
			reg = <0x40007000 0x400>;
		};

		rcc: rcc@40023810 {
			#reset-cells = <1>;
			#clock-cells = <2>;
			compatible = "st,stm32f746-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>;
			st,syscfg = <&pwrcfg>;
			u-boot,dm-pre-reloc;
		};

		pinctrl: pin-controller {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32f746-pinctrl";
			ranges = <0 0x40020000 0x3000>;
			u-boot,dm-pre-reloc;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x0 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
				st,bank-name = "GPIOA";
				u-boot,dm-pre-reloc;
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
				st,bank-name = "GPIOB";
				u-boot,dm-pre-reloc;
			};


			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
				st,bank-name = "GPIOC";
				u-boot,dm-pre-reloc;
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
				st,bank-name = "GPIOD";
				u-boot,dm-pre-reloc;
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
				st,bank-name = "GPIOE";
				u-boot,dm-pre-reloc;
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
				st,bank-name = "GPIOF";
				u-boot,dm-pre-reloc;
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
				st,bank-name = "GPIOG";
				u-boot,dm-pre-reloc;
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
				st,bank-name = "GPIOH";
				u-boot,dm-pre-reloc;
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
				st,bank-name = "GPIOI";
				u-boot,dm-pre-reloc;
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
				st,bank-name = "GPIOJ";
				u-boot,dm-pre-reloc;
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				compatible = "st,stm32-gpio";
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
				st,bank-name = "GPIOK";
				u-boot,dm-pre-reloc;
			};

			sdio_pins: sdio_pins@0 {
				pins {
					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
						 <STM32F746_PC12_FUNC_SDMMC1_CK>,
						 <STM32F746_PD2_FUNC_SDMMC1_CMD>;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			sdio_pins_od: sdio_pins_od@0 {
				pins1 {
					pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
						 <STM32F746_PC9_FUNC_SDMMC1_D1>,
						 <STM32F746_PC10_FUNC_SDMMC1_D2>,
						 <STM32F746_PC11_FUNC_SDMMC1_D3>,
						 <STM32F746_PC12_FUNC_SDMMC1_CK>;
					drive-push-pull;
					slew-rate = <2>;
				};

				pins2 {
					pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
					drive-open-drain;
					slew-rate = <2>;
				};
			};

			sdio_pins_b: sdio_pins_b@0 {
				pins {
					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
						 <STM32F769_PD6_FUNC_SDMMC2_CLK>,
						 <STM32F769_PD7_FUNC_SDMMC2_CMD>;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			sdio_pins_od_b: sdio_pins_od_b@0 {
				pins1 {
					pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
						 <STM32F769_PG10_FUNC_SDMMC2_D1>,
						 <STM32F769_PB3_FUNC_SDMMC2_D2>,
						 <STM32F769_PB4_FUNC_SDMMC2_D3>,
						 <STM32F769_PD6_FUNC_SDMMC2_CLK>;
					drive-push-pull;
					slew-rate = <2>;
				};

				pins2 {
					pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
					drive-open-drain;
					slew-rate = <2>;
				};
			};

		};
		sdio: sdio@40012c00 {
			compatible = "st,stm32f4xx-sdio";
			reg = <0x40012c00 0x400>;
			clocks = <&rcc 0 171>;
			interrupts = <49>;
			status = "disabled";
			pinctrl-0 = <&sdio_pins>;
			pinctrl-1 = <&sdio_pins_od>;
			pinctrl-names = "default", "opendrain";
			max-frequency = <48000000>;
		};

		sdio2: sdio2@40011c00 {
			compatible = "st,stm32f4xx-sdio";
			reg = <0x40011c00 0x400>;
			clocks = <&rcc 0 167>;
			interrupts = <103>;
			status = "disabled";
			pinctrl-0 = <&sdio_pins_b>;
			pinctrl-1 = <&sdio_pins_od_b>;
			pinctrl-names = "default", "opendrain";
			max-frequency = <48000000>;
		};

		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
		};

		ltdc: display-controller@40016800 {
			compatible = "st,stm32-ltdc";
			reg = <0x40016800 0x200>;
			resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
			clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
			u-boot,dm-pre-reloc;
			status = "disabled";
		};
	};
};

&systick {
	status = "okay";
};