arm/dts/stm32f429.dtsi

47 #include <dt-bindings/mfd/stm32f4-rcc.h>
81 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
220 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
229 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
245 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
265 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
279 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
292 			clocks = <&rcc 1 CLK_RTC>;
294 			assigned-clocks = <&rcc 1 CLK_RTC>;
295 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
314 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
322 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
333 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
341 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
350 			resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
351 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
360 			resets = <&rcc STM32F4_APB1_RESET(DAC)>;
361 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
386 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
394 			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
403 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
424 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
444 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
455 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
463 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
475 				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
487 				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
499 				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
526 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
546 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
560 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
578 			clocks = <&rcc 0 171>;
591 			resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
592 			clocks = <&rcc 1 CLK_LCD>;
600 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
604 		rcc: rcc@40023810 {  label
607 			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
611 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
626 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
641 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
653 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
654 					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
655 					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
666 			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
675 			clocks = <&rcc 0 39>;
684 			resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
685 			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
698 			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
705 	clocks = <&rcc 1 SYSTICK>;