Lines Matching refs:rcc

141 			clocks = <&rcc TIM2_K>;
162 			clocks = <&rcc TIM3_K>;
183 			clocks = <&rcc TIM4_K>;
204 			clocks = <&rcc TIM5_K>;
225 			clocks = <&rcc TIM6_K>;
241 			clocks = <&rcc TIM7_K>;
257 			clocks = <&rcc TIM12_K>;
278 			clocks = <&rcc TIM13_K>;
299 			clocks = <&rcc TIM14_K>;
320 			clocks = <&rcc LPTIM1_K>;
346 			clocks = <&rcc USART2_K>;
354 			clocks = <&rcc USART3_K>;
362 			clocks = <&rcc UART4_K>;
370 			clocks = <&rcc UART5_K>;
380 			clocks = <&rcc I2C1_K>;
381 			resets = <&rcc I2C1_R>;
393 			clocks = <&rcc I2C2_K>;
394 			resets = <&rcc I2C2_R>;
406 			clocks = <&rcc I2C3_K>;
407 			resets = <&rcc I2C3_R>;
419 			clocks = <&rcc I2C5_K>;
420 			resets = <&rcc I2C5_R>;
430 			clocks = <&rcc CEC_K>, <&clk_lse>;
438 			clocks = <&rcc DAC12>;
463 			clocks = <&rcc UART7_K>;
471 			clocks = <&rcc UART8_K>;
480 			clocks = <&rcc TIM1_K>;
501 			clocks = <&rcc TIM8_K>;
521 			clocks = <&rcc USART6_K>;
530 			clocks = <&rcc TIM15_K>;
551 			clocks = <&rcc TIM16_K>;
571 			clocks = <&rcc TIM17_K>;
598 			clocks = <&rcc DMA1>;
615 			clocks = <&rcc DMA2>;
628 			clocks = <&rcc DMAMUX>;
636 			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
668 			clocks = <&rcc SDMMC3_K>;
669 			resets = <&rcc SDMMC3_R>;
680 			clocks = <&rcc USBO_K>;
682 			resets = <&rcc USBO_R>;
697 			clocks = <&rcc HSEM>;
702 		rcc: rcc@50000000 {  label
703 			compatible = "st,stm32mp1-rcc", "syscon";
709 		rcc_reboot: rcc-reboot@50000000 {
711 			regmap = <&rcc>;
721 			st,sysrcc = <&rcc>;
722 			clocks = <&rcc PLL2_R>;
727 				st,tzcr = <&rcc 0x0 0x1>;
766 			clocks = <&rcc LPTIM2_K>;
793 			clocks = <&rcc LPTIM3_K>;
813 			clocks = <&rcc LPTIM4_K>;
827 			clocks = <&rcc LPTIM5_K>;
843 			clocks = <&rcc VREF>;
851 			clocks = <&rcc CRYP1>;
852 			resets = <&rcc CRYP1_R>;
859 			clocks = <&rcc RNG1_K>;
860 			resets = <&rcc RNG1_R>;
868 			clocks = <&rcc MDMA>;
879 			clocks = <&rcc QSPI_K>;
880 			resets = <&rcc QSPI_R>;
888 			clocks = <&rcc SDMMC1_K>;
889 			resets = <&rcc SDMMC1_R>;
902 			clocks = <&rcc SDMMC2_K>;
903 			resets = <&rcc SDMMC2_R>;
914 			clocks = <&rcc CRC1>;
921 			clocks = <&rcc USBH>;
922 			resets = <&rcc USBH_R>;
930 			clocks = <&rcc USBH>;
931 			resets = <&rcc USBH_R>;
940 			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
942 			resets = <&rcc DSI_R>;
952 			clocks = <&rcc LTDC_PX>;
954 			resets = <&rcc LTDC_R>;
963 			clocks = <&rcc USBPHY_K>;
964 			resets = <&rcc USBPHY_R>;
982 			clocks = <&rcc USART1_K>;
992 			clocks = <&rcc I2C4_K>;
993 			resets = <&rcc I2C4_R>;
1005 			clocks = <&rcc I2C6_K>;
1006 			resets = <&rcc I2C6_R>;