Lines Matching refs:rcc
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
269 clocks = <&rcc 1 CLK_RTC>;
270 assigned-clocks = <&rcc 1 CLK_RTC>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
292 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
310 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
318 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
346 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
358 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
370 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
388 resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
389 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
398 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
399 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
424 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
432 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
441 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
463 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
503 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
515 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
527 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
539 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
552 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
597 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
617 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
631 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
648 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
661 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
674 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
675 clocks = <&rcc 1 CLK_LCD>;
683 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
687 rcc: rcc@40023800 { label
690 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
694 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
709 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
724 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
736 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
737 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
738 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
749 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
750 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
759 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
768 clocks = <&rcc 0 39>;
777 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
778 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
790 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
797 clocks = <&rcc 1 SYSTICK>;