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Searched refs:deposit32 (Results 1 – 25 of 100) sorted by relevance

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/openbmc/qemu/hw/mips/
H A Dbootloader.c90 insn = deposit32(insn, 26, 6, opcode); in bl_gen_r_type()
91 insn = deposit32(insn, 21, 5, rs); in bl_gen_r_type()
92 insn = deposit32(insn, 16, 5, rt); in bl_gen_r_type()
93 insn = deposit32(insn, 11, 5, rd); in bl_gen_r_type()
94 insn = deposit32(insn, 6, 5, shift); in bl_gen_r_type()
95 insn = deposit32(insn, 0, 6, funct); in bl_gen_r_type()
109 insn = deposit32(insn, 26, 6, opcode); in bl_gen_i_type()
110 insn = deposit32(insn, 21, 5, rs); in bl_gen_i_type()
111 insn = deposit32(insn, 16, 5, rt); in bl_gen_i_type()
112 insn = deposit32(insn, 0, 16, imm); in bl_gen_i_type()
[all …]
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc241 tcg_patch32(code_ptr, deposit32(*code_ptr, 32 - type, type, diff));
261 insn = deposit32(insn, 0, 8, op);
280 insn = deposit32(insn, 0, 8, op);
281 insn = deposit32(insn, 12, 20, diff);
289 insn = deposit32(insn, 0, 8, op);
290 insn = deposit32(insn, 8, 4, r0);
304 insn = deposit32(insn, 0, 8, op);
305 insn = deposit32(insn, 8, 4, r0);
306 insn = deposit32(insn, 12, 20, i1);
315 insn = deposit32(insn, 0, 8, op);
[all …]
/openbmc/qemu/hw/misc/
H A Dgrlib_ahb_apb_pnp.c110 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_ahb_pnp_add_entry()
114 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_ahb_pnp_add_entry()
121 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_ahb_pnp_add_entry()
127 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_ahb_pnp_add_entry()
215 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_apb_pnp_add_entry()
219 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_apb_pnp_add_entry()
223 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_apb_pnp_add_entry()
227 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_apb_pnp_add_entry()
233 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_apb_pnp_add_entry()
239 dev->regs[reg_start] = deposit32(dev->regs[reg_start], in grlib_apb_pnp_add_entry()
H A Diotkit-secctl.c635 s->mpcintstatus = deposit32(s->mpcintstatus, n, 1, !!level); in iotkit_secctl_mpc_status()
642 s->mpcintstatus = deposit32(s->mpcintstatus, n + 16, 1, !!level); in iotkit_secctl_mpcexp_status()
649 s->secmscintstat = deposit32(s->secmscintstat, n + 16, 1, !!level); in iotkit_secctl_mscexp_status()
659 s->secppcintstat = deposit32(s->secppcintstat, irqbit, 1, level); in iotkit_secctl_ppc_irqstatus()
/openbmc/qemu/include/hw/
H A Dregisterfields.h90 _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
98 _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
106 _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
123 _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
131 _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
139 _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
194 _d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
202 _d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
210 _d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
/openbmc/qemu/hw/gpio/
H A Daspeed_gpio.c288 regs->int_status = deposit32(regs->int_status, gpio, 1, 1); in aspeed_evaluate_irq()
689 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
699 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
719 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
724 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
729 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
734 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
753 set->int_status = deposit32(set->int_status, pin_idx, 1, 0); in aspeed_gpio_write_index_mode()
758 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
763 reg_value = deposit32(reg_value, pin_idx, 1, in aspeed_gpio_write_index_mode()
[all …]
H A Dnrf51_gpio.c71 s->old_out = deposit32(s->old_out, i, 1, level); in update_output_irq()
72 s->old_out_connected = deposit32(s->old_out_connected, i, 1, connected); in update_output_irq()
94 s->in = deposit32(s->in, i, 1, pull); in update_state()
121 s->in = deposit32(s->in, i, 1, out); in update_state()
253 s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); in nrf51_gpio_set()
255 s->in = deposit32(s->in, line, 1, value != 0); in nrf51_gpio_set()
H A Dsifive_gpio.c88 s->high_ip = deposit32(s->high_ip, i, 1, high_ip); in update_state()
91 s->low_ip = deposit32(s->low_ip, i, 1, low_ip); in update_state()
94 s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip); in update_state()
97 s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip); in update_state()
100 s->value = deposit32(s->value, i, 1, ival); in update_state()
292 s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); in sifive_gpio_set()
294 s->in = deposit32(s->in, line, 1, value != 0); in sifive_gpio_set()
H A Dimx_gpio.c91 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
98 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
104 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
117 s->psr = deposit32(s->psr, line, 1, imx_level); in imx_gpio_set()
H A Dnpcm7xx_gpio.c337 s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0); in npcm7xx_gpio_set_input()
338 s->ext_level = deposit32(s->ext_level, line, 1, level > 0); in npcm7xx_gpio_set_input()
/openbmc/qemu/hw/arm/
H A Dsmmuv3-internal.h257 q->cons = deposit32(q->cons, 0, q->log2size + 1, q->cons + 1); in queue_cons_incr()
504 #define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
505 #define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
506 #define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
508 #define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
509 #define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
510 #define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
511 #define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
512 #define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
513 #define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
[all …]
H A Darmsse.c586 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
587 sys_config = deposit32(sys_config, 4, 4, s->sram_addr_width - 12); in armsse_sys_config_value()
591 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
592 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); in armsse_sys_config_value()
593 sys_config = deposit32(sys_config, 24, 4, 2); in armsse_sys_config_value()
595 sys_config = deposit32(sys_config, 10, 1, 1); in armsse_sys_config_value()
596 sys_config = deposit32(sys_config, 20, 4, info->sram_banks - 1); in armsse_sys_config_value()
597 sys_config = deposit32(sys_config, 28, 4, 2); in armsse_sys_config_value()
602 sys_config = deposit32(sys_config, 0, 4, info->sram_banks); in armsse_sys_config_value()
603 sys_config = deposit32(sys_config, 4, 5, s->sram_addr_width); in armsse_sys_config_value()
[all …]
/openbmc/qemu/target/tricore/
H A Dfpu_helper.c238 result = deposit32(result, 31, 1, new_S); in helper_qseed()
239 result = deposit32(result, 23, 8, new_E); in helper_qseed()
240 result = deposit32(result, 15, 8, new_M); in helper_qseed()
393 result = deposit32(result, 23, 8, 0xff); in helper_hptof()
394 result = deposit32(result, 21, 2, extract32(f_arg, 8, 2)); in helper_hptof()
395 result = deposit32(result, 0, 8, extract32(f_arg, 0, 8)); in helper_hptof()
428 result = deposit32(result, 10, 5, 0x1f); in helper_ftohp()
429 result = deposit32(result, 8, 2, extract32(arg, 21, 2)); in helper_ftohp()
430 result = deposit32(result, 0, 8, extract32(arg, 0, 8)); in helper_ftohp()
/openbmc/qemu/target/riscv/
H A Dinstmap.h323 #define SET_RS1(inst, val) deposit32(inst, 15, 5, val)
324 #define SET_RS2(inst, val) deposit32(inst, 20, 5, val)
325 #define SET_RD(inst, val) deposit32(inst, 7, 5, val)
326 #define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val)
328 deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5)
/openbmc/qemu/target/arm/
H A Dvfp_helper.c427 return deposit32(lo, 16, 16, hi); in HELPER()
630 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); in call_recip_estimate()
707 f16_val = deposit32(0, 15, 1, f16_sign); in HELPER()
708 f16_val = deposit32(f16_val, 10, 5, f16_exp); in HELPER()
709 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); in HELPER()
757 f32_val = deposit32(0, 31, 1, f32_sign); in HELPER()
758 f32_val = deposit32(f32_val, 23, 8, f32_exp); in HELPER()
759 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); in HELPER()
853 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); in recip_sqrt_estimate()
856 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); in recip_sqrt_estimate()
[all …]
H A Dhyp_gdbstub.c68 brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */ in insert_hw_breakpoint()
69 brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */ in insert_hw_breakpoint()
167 wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas); in insert_hw_watchpoint()
H A Dcpu-features.h1065 ccsidr = deposit32(ccsidr, 28, 4, flags); in make_ccsidr()
1066 ccsidr = deposit32(ccsidr, 13, 15, sets - 1); in make_ccsidr()
1067 ccsidr = deposit32(ccsidr, 3, 10, assoc - 1); in make_ccsidr()
1068 ccsidr = deposit32(ccsidr, 0, 3, lg_linesize - 4); in make_ccsidr()
/openbmc/qemu/hw/display/
H A Ddm163.c127 rgba = deposit32(rgba, 0, 8, r); in dm163_propagate_outputs()
128 rgba = deposit32(rgba, 8, 8, g); in dm163_propagate_outputs()
129 rgba = deposit32(rgba, 16, 8, b); in dm163_propagate_outputs()
179 val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word); in dm163_bank0()
180 val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word, in dm163_bank0()
/openbmc/qemu/target/xtensa/
H A Dop_helper.c180 deposit32(v, MEMCTL_IUSEWAYS_SHIFT, MEMCTL_IUSEWAYS_LEN, in HELPER()
187 deposit32(v, MEMCTL_DUSEWAYS_SHIFT, MEMCTL_DUSEWAYS_LEN, in HELPER()
192 deposit32(v, MEMCTL_DALLOCWAYS_SHIFT, MEMCTL_DALLOCWAYS_LEN, in HELPER()
/openbmc/qemu/hw/timer/
H A Dcmsdk-apb-dualtimer.c177 load = deposit32(m->load, 0, 16, load); in cmsdk_dualtimermod_write_control()
196 value = deposit32(m->value, 0, 16, value); in cmsdk_dualtimermod_write_control()
206 load = deposit32(m->load, 0, 16, load); in cmsdk_dualtimermod_write_control()
280 r = deposit32(m->load, 0, 16, r); in cmsdk_apb_dualtimer_read()
290 r = deposit32(m->value, 0, 16, r); in cmsdk_apb_dualtimer_read()
/openbmc/qemu/hw/net/can/
H A Dxlnx-zynqmp-can.c735 fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT, in update_rx_fifo()
738 deposit32(0, R_RXFIFO_DLC_RXT_SHIFT, in update_rx_fifo()
743 fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA1_DB3_SHIFT, in update_rx_fifo()
746 deposit32(0, R_RXFIFO_DATA1_DB2_SHIFT, in update_rx_fifo()
749 deposit32(0, R_RXFIFO_DATA1_DB1_SHIFT, in update_rx_fifo()
752 deposit32(0, R_RXFIFO_DATA1_DB0_SHIFT, in update_rx_fifo()
756 fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DATA2_DB7_SHIFT, in update_rx_fifo()
759 deposit32(0, R_RXFIFO_DATA2_DB6_SHIFT, in update_rx_fifo()
762 deposit32(0, R_RXFIFO_DATA2_DB5_SHIFT, in update_rx_fifo()
765 deposit32(0, R_RXFIFO_DATA2_DB4_SHIFT, in update_rx_fifo()
/openbmc/qemu/hw/block/
H A Dpflash_cfi01.c181 resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]); in pflash_cfi_query()
188 resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); in pflash_cfi_query()
240 resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); in pflash_devid_query()
344 ret = deposit32(ret, i * 8, pfl->bank_width * 8, in pflash_read()
372 ret = deposit32(ret, i * 8, pfl->bank_width * 8, in pflash_read()
/openbmc/qemu/linux-user/s390x/
H A Dtarget_proc.h43 return deposit32(0, CPU_ID_BITS - CPU_PHYS_ADDR_BITS, CPU_PHYS_ADDR_BITS, in cpu_ident()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c195 pend = deposit32(pend, irq % 8, 1, level ? 1 : 0); in set_pending_table_bit()
1144 cs->level = deposit32(cs->level, irq, 1, level); in gicv3_redist_set_irq()
1149 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1); in gicv3_redist_set_irq()
1185 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 1); in gicv3_redist_send_sgi()
/openbmc/qemu/target/hexagon/
H A Dgdbstub.c30 p3_0 = deposit32(p3_0, i * 8, 8, env->pred[i]); in hexagon_gdb_read_register()

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