Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into staging

aspeed queue:

* Extra avocado tests using buildroot images
* Conversion of the I2C model to the registerfield inter

Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into staging

aspeed queue:

* Extra avocado tests using buildroot images
* Conversion of the I2C model to the registerfield interface
* Support for the I2C new register interface on AST2600
* Various I2C enhancements
* I2C support for the AST1030
* Improvement of the Aspeed SMC and m25p80 qtest

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmKyzCYACgkQUaNDx8/7
# 7KG+Aw/+MM3BlQfzDhjETkznqFbvp+aDcnKYwd/brizUC1y3paPFGc0xzD05x3QC
# 2th44oYS934UwQ78EMkC0uNed/kHh+6aHaBrq/XylIg7Dbq5QeCBXwRGCNW6tgtc
# K3ZSM20QM+XRCjmo9ys792NYPC+8tYpw7idb2AOeum7ic/ZaeT3h1FX1Mr57I3XE
# PYwDEBEd4hJ3DroYzIP9YQvRBNu8/d5VoiNr3GLfNy3zrkhuJ4D4jUAEbHATG7Gb
# k0A6o6bVAL85AUSq/ksceHqzWAnizh1q1o/k9UP83HIt1S3ghgK6RsAu4+9HKlP4
# lZ6MFfx3Nzf8u2y/FlOiuABEBUNsngjNmLo6B/qe/cZk60/nS56qOWSvuzPxqVDO
# lI++SLY6R1D8q36H4eF/vq/AyLnXBxGqeq0DipPcnZVKdVVHUHppNly5efJ/7cWn
# VybobblU48BCgjc/EoMVEy8L/t/uRjY3wmoKkfKLCObRrlcPxSrLPUP8+j8nR0JG
# zDOh+CrxHTUbJGV6qRmZx9m2HQtbtH5k89UxskkUkscvVDqWhxqdFVnTWfXcmyP8
# LqTkEv7IV4ECM1zN5OVK9No46WCi5j24bxO3z7or4e04vgwjM41unV7HAFl8Z0/s
# tyFQUG4dFAKHH7quU0F3qSxnORNyCy5ssEpmobujeifbiFMpNss=
# =OsUe
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 22 Jun 2022 01:00:38 AM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu:
hw: m25p80: fixing individual test failure when tests are running in isolation
aspeed/hace: Add missing newlines to unimp messages
aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH always
hw/i2c/aspeed: add DEV_ADDR in old register mode
hw/i2c/aspeed: rework raise interrupt trace event
aspeed: Add I2C buses to AST1030 model
aspeed/i2c: Add ast1030 controller models
aspeed: i2c: Move regs and helpers to header file
aspeed: i2c: Add PKT_DONE IRQ to trace
aspeed: i2c: Add new mode support
aspeed: i2c: Use reg array instead of individual vars
aspeed: i2c: Migrate to registerfields API
hw/registerfields: Add shared fields macros
test/avocado/machine_aspeed.py: Add an I2C RTC test
test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evb
test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evb
test/avocado/machine_aspeed.py: Add tests using buildroot images
test/avocado/machine_aspeed.py: Move OpenBMC tests
aspeed: Remove fake RTC device on ast2500-evb

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/registerfields: Add shared fields macros

Occasionally a peripheral will have different operating modes, where the
MMIO layout changes, but some of the register fields have the same offsets
and be

hw/registerfields: Add shared fields macros

Occasionally a peripheral will have different operating modes, where the
MMIO layout changes, but some of the register fields have the same offsets
and behaviors.

To help support this, we add SHARED_FIELD_XX macros that create SHIFT,
LENGTH, and MASK macros for the fields that are shared across registers,
and accessors for these fields.

An example use may look as follows:
There is a peripheral with registers REG_MODE1 and REG_MODE2 at
different addreses, and both have a field FIELD1 initialized by
SHARED_FIELD().

Depending on what mode the peripheral is operating in, the user could
extract FIELD1 via
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE1, FIELD1)
or
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE2, FIELD1)

Signed-off-by: Joe Komlodi <komlodi@google.com>
Change-Id: Id3dc53e7d2f8741c95697cbae69a81bb699fa3cb
Message-Id: <20220331043248.2237838-2-komlodi@google.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220302' into staging

target-arm queue:
* mps3-an547: Add missing user ahb interfaces
* hw/arm/mps2-tz.c: Update AN547 document

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220302' into staging

target-arm queue:
* mps3-an547: Add missing user ahb interfaces
* hw/arm/mps2-tz.c: Update AN547 documentation URL
* hw/input/tsc210x: Don't abort on bad SPI word widths
* hw/i2c: flatten pca954x mux device
* target/arm: Support PSCI 1.1 and SMCCC 1.0
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
* tests/qtest: add qtests for npcm7xx sdhci
* Implement FEAT_LVA
* Implement FEAT_LPA
* Implement FEAT_LPA2 (but do not enable it yet)
* Report KVM's actual PSCI version to guest in dtb
* ui/cocoa.m: Fix updateUIInfo threading issues
* ui/cocoa.m: Remove unnecessary NSAutoreleasePools

# gpg: Signature made Wed 02 Mar 2022 20:52:06 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20220302: (26 commits)
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
ui/cocoa.m: Fix updateUIInfo threading issues
target/arm: Report KVM's actual PSCI version to guest in dtb
target/arm: Implement FEAT_LPA2
target/arm: Advertise all page sizes for -cpu max
target/arm: Validate tlbi TG matches translation granule in use
target/arm: Fix TLBIRange.base for 16k and 64k pages
target/arm: Introduce tlbi_aa64_get_range
target/arm: Extend arm_fi_to_lfsc to level -1
target/arm: Implement FEAT_LPA
target/arm: Implement FEAT_LVA
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
target/arm: Honor TCR_ELx.{I}PS
target/arm: Use MAKE_64BIT_MASK to compute indexmask
target/arm: Pass outputsize down to check_s2_mmu_setup
target/arm: Move arm_pamax out of line
target/arm: Fault on invalid TCR_ELx.TxSZ
target/arm: Set TCR_EL1.TSZ for user-only
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
tests/qtest: add qtests for npcm7xx sdhci
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>

Add new macros to manipulate signed fields within the register.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Hen

hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>

Add new macros to manipulate signed fields within the register.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-2-richard.henderson@linaro.org
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging

First RISC-V PR for QEMU 6.2

- Add a config for Shakti UART
- Fixup virt flash node
- Don't overr

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging

First RISC-V PR for QEMU 6.2

- Add a config for Shakti UART
- Fixup virt flash node
- Don't override users supplied ISA version
- Fixup some CSR accesses
- Use g_strjoinv() for virt machine PLIC string config
- Fix an overflow in the SiFive CLINT
- Add 64-bit register access helpers
- Replace tcg_const_* with direct constant usage

# gpg: Signature made Wed 01 Sep 2021 03:08:48 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210901-2: (33 commits)
target/riscv: Use {get,dest}_gpr for RVV
target/riscv: Tidy trans_rvh.c.inc
target/riscv: Use {get,dest}_gpr for RVD
target/riscv: Use {get,dest}_gpr for RVF
target/riscv: Use gen_shift_imm_fn for slli_uw
target/riscv: Use {get,dest}_gpr for RVA
target/riscv: Reorg csr instructions
target/riscv: Fix hgeie, hgeip
target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
target/riscv: Use {get, dest}_gpr for integer load/store
target/riscv: Use get_gpr in branches
target/riscv: Use extracts for sraiw and srliw
target/riscv: Use DisasExtend in shift operations
target/riscv: Add DisasExtend to gen_unary
target/riscv: Move gen_* helpers for RVB
target/riscv: Move gen_* helpers for RVM
target/riscv: Use gen_arith for mulh and mulhu
target/riscv: Remove gen_arith_div*
target/riscv: Add DisasExtend to gen_arith*
target/riscv: Introduce DisasExtend and new helpers
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/registerfields: Use 64-bit bitfield for FIELD_DP64

If we have a field that's wider than 32-bits, we need a data type wide enough to
be able to create the bitfield used to deposit the value.

Sign

hw/registerfields: Use 64-bit bitfield for FIELD_DP64

If we have a field that's wider than 32-bits, we need a data type wide enough to
be able to create the bitfield used to deposit the value.

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

hw/core/register: Add more 64-bit utilities

We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositi

hw/core/register: Add more 64-bit utilities

We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositing to an array of 64-bit registers

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge remote-tracking branch 'remotes/alistair/tags/pull-register-api-20200527' into staging

A single patch to avoid clashes with the regiser field macros.

# gpg: Signature made Wed 27 May 2020 19:

Merge remote-tracking branch 'remotes/alistair/tags/pull-register-api-20200527' into staging

A single patch to avoid clashes with the regiser field macros.

# gpg: Signature made Wed 27 May 2020 19:24:07 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-register-api-20200527:
hw/registerfields: Prefix local variables with underscore in macros

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/registerfields: Prefix local variables with underscore in macros

One can name a local variable holding a value as 'v', but it
currently clashes with the registerfields macros. To save others
to d

hw/registerfields: Prefix local variables with underscore in macros

One can name a local variable holding a value as 'v', but it
currently clashes with the registerfields macros. To save others
to debug the same mistake, prefix the macro's local variables
with an underscore.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200510203457.10546-1-f4bug@amsat.org
Message-Id: <20200510203457.10546-1-f4bug@amsat.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging

Introduce the architectural part of the Renesas RX
architecture emulation, developed by Yoshinori Sa

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging

Introduce the architectural part of the Renesas RX
architecture emulation, developed by Yoshinori Sato.

CI jobs results:
https://gitlab.com/philmd/qemu/pipelines/127886344
https://travis-ci.org/github/philmd/qemu/builds/664579420

# gpg: Signature made Fri 20 Mar 2020 10:27:32 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/target_renesas_rx-20200320:
Add rx-softmmu
target/rx: Dump bytes for each insn during disassembly
target/rx: Collect all bytes during disassembly
target/rx: Emit all disassembly in one prt()
target/rx: Use prt_ldmi for XCHG_mr disassembly
target/rx: Replace operand with prt_ldmi in disassembler
target/rx: Disassemble rx_index_addr into a string
target/rx: RX disassembler
target/rx: CPU definitions
target/rx: TCG helpers
target/rx: TCG translation
MAINTAINERS: Add entry for the Renesas RX architecture
hw/registerfields.h: Add 8bit and 16bit register macros

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/registerfields.h: Add 8bit and 16bit register macros

Some RX peripheral use 8bit and 16bit registers.
Add the 8bit and 16bit APIs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
R

hw/registerfields.h: Add 8bit and 16bit register macros

Some RX peripheral use 8bit and 16bit registers.
Add the 8bit and 16bit APIs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200224141923.82118-4-ysato@users.sourceforge.jp>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...

Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-02-07-v4' into staging

Miscellaneous patches for 2018-02-07

# gpg: Signature made Fri 09 Feb 2018 12:52:51 GMT
# gpg:

Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-02-07-v4' into staging

Miscellaneous patches for 2018-02-07

# gpg: Signature made Fri 09 Feb 2018 12:52:51 GMT
# gpg: using RSA key 3870B400EB918653
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>"
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>"
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-misc-2018-02-07-v4:
Move include qemu/option.h from qemu-common.h to actual users
Drop superfluous includes of qapi/qmp/qjson.h
Drop superfluous includes of qapi/qmp/dispatch.h
Include qapi/qmp/qnull.h exactly where needed
Include qapi/qmp/qnum.h exactly where needed
Include qapi/qmp/qbool.h exactly where needed
Include qapi/qmp/qstring.h exactly where needed
Include qapi/qmp/qdict.h exactly where needed
Include qapi/qmp/qlist.h exactly where needed
Include qapi/qmp/qobject.h exactly where needed
qdict qlist: Make most helper macros functions
Eliminate qapi/qmp/types.h
Typedef the subtypes of QObject in qemu/typedefs.h, too
Include qmp-commands.h exactly where needed
Drop superfluous includes of qapi/qmp/qerror.h
Include qapi/error.h exactly where needed
Drop superfluous includes of qapi-types.h and test-qapi-types.h
Clean up includes
Use #include "..." for our own headers, <...> for others
vnc: use stubs for CONFIG_VNC=n dummy functions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Use #include "..." for our own headers, <...> for others

System headers should be included with <...>, our own headers with
"...". Offenders tracked down with an ugly, brittle and probably
buggy Pe

Use #include "..." for our own headers, <...> for others

System headers should be included with <...>, our own headers with
"...". Offenders tracked down with an ugly, brittle and probably
buggy Perl script. Previous iteration was commit a9c94277f0.

Delete inclusions of "string.h" and "strings.h" instead of fixing them
to <string.h> and <strings.h>, because we always include these via
osdep.h.

Put the cleaned up system header includes first.

While there, separate #include from file comment with exactly one
blank line.

Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20180201111846.21846-2-armbru@redhat.com>

show more ...

Merge remote-tracking branch 'origin/master' into HEAD

Resolve conflicts around apb.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging

trivial patches for 2017-12-18

# gpg: Signature made Mon 18 Dec 2017 14:08:51 GMT
# gpg: using RSA

Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging

trivial patches for 2017-12-18

# gpg: Signature made Mon 18 Dec 2017 14:08:51 GMT
# gpg: using RSA key 0x701B4F6B1A693E59
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg: aka "Michael Tokarev <mjt@corpit.ru>"
# gpg: aka "Michael Tokarev <mjt@debian.org>"
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5
# Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59

* remotes/mjt/tags/trivial-patches-fetch: (60 commits)
misc: drop old i386 dependency
i386/pc: move vmmouse.c to hw/i386/
i386/pc: move vmport.c to hw/i386/
hw/misc/pvpanic: extract public API from i386/pc to "hw/misc/pvpanic.h"
hw/net/ne2000: extract ne2k-isa code from i386/pc to ne2000-isa.c
hw/display/vga: extract public API from i386/pc to "hw/display/vga.h"
hw/display/vga: "vga_int.h" requires "ui/console.h"
hw/display/vga: "vga.h" only contains registers defs, rename it "vga_regs.h"
hw/acpi/ich9: extract ACPI_PM_PROP_TCO_ENABLED from i386/pc
hw/acpi: ACPI_PM_* defines are not restricted to i386 arch
hw/timer/mc146818: rename rtc_init() -> mc146818_rtc_init()
hw/timer/i8254: rename pit_init() -> i8254_pit_init()
hw/unicore32: restrict hw addr defines to source file
hw/virtio-balloon: remove old i386 dependency
hw/tpm: remove old i386 dependency
hw/i2c: remove old i386 dependency
hw/ipmi: remove old i386 dependency
hw/ide: remove old i386 dependency
misc: remove old i386 dependency
amd_iommu: avoid needless includes in header file
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/registerfields: add missing include

This allows to use this header in qtests.

This fixes:
CC tests/test.o
include/hw/registerfields.h:32:41: error: implicit declaration of function ‘M

hw/registerfields: add missing include

This allows to use this header in qtests.

This fixes:
CC tests/test.o
include/hw/registerfields.h:32:41: error: implicit declaration of function ‘MAKE_64BIT_MASK’ [-Werror=implicit-function-declaration]
MAKE_64BIT_MASK(shift, length)};
^
include/hw/registerfields.h:39:5: error: implicit declaration of function ‘extract64’; [-Werror=implicit-function-declaration]
extract64((storage), R_ ## reg ## _ ## field ## _SHIFT,
^

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

show more ...

hw/registerfields: add 64-bit extract/deposit macros

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <alista

hw/registerfields: add 64-bit extract/deposit macros

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

show more ...

hw/registerfields: fix a typo in the FIELD() documentation

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <

hw/registerfields: fix a typo in the FIELD() documentation

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170127' into staging

target-arm queue:
* various minor M profile bugfixes
* aspeed/smc: handle dummy bytes when doing fast rea

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170127' into staging

target-arm queue:
* various minor M profile bugfixes
* aspeed/smc: handle dummy bytes when doing fast reads in command mode
* pflash_cfi01: fix per-device sector length in CFI table
* arm: stellaris: make MII accesses complete immediately
* hw/char/exynos4210_uart: Drop unused local variable frame_size
* arm_gicv3: Fix broken logic in ELRSR calculation
* dma: omap: check dma channel data_type

# gpg: Signature made Fri 27 Jan 2017 15:29:39 GMT
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170127: (22 commits)
dma: omap: check dma channel data_type
arm_gicv3: Fix broken logic in ELRSR calculation
hw/char/exynos4210_uart: Drop unused local variable frame_size
arm: stellaris: make MII accesses complete immediately
armv7m: R14 should reset to 0xffffffff
armv7m: FAULTMASK should be 0 on reset
armv7m: Honour CCR.USERSETMPEND
armv7m: Report no-coprocessor faults correctly
armv7m: set CFSR.UNDEFINSTR on undefined instructions
armv7m: honour CCR.STACKALIGN on exception entry
armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR
armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR
armv7m_nvic: keep a pointer to the CPU
target/arm: Drop IS_M() macro
pflash_cfi01: fix per-device sector length in CFI table
armv7m: Clear FAULTMASK on return from non-NMI exceptions
armv7m: Fix reads of CONTROL register bit 1
hw/registerfields.h: Pull FIELD etc macros out of hw/register.h
armv7m: Explicit error for bad vector table
armv7m: Replace armv7m.hack with unassigned_access handler
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/registerfields.h: Pull FIELD etc macros out of hw/register.h

hw/register.h provides macros like FIELD which make it easy to define
shift, mask and length constants for the fields within a registe

hw/registerfields.h: Pull FIELD etc macros out of hw/register.h

hw/register.h provides macros like FIELD which make it easy to define
shift, mask and length constants for the fields within a register.
Unfortunately register.h also includes a lot of other things, some
of which will only compile in the softmmu build.

Pull the FIELD macro and friends out into a separate header file,
so they can be used in places like target/arm files which also
get built in the user-only configs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1484937883-1068-5-git-send-email-peter.maydell@linaro.org

show more ...