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Searched refs:PRV_M (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dop_helper.c138 if ((env->priv < PRV_M) && !get_field(env->menvcfg, envbits)) { in check_zicbo_envcfg()
276 if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { in helper_sret()
326 if (!(env->priv >= PRV_M)) { in helper_mret()
339 !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { in helper_mret()
344 (prev_priv != PRV_M); in helper_mret()
349 riscv_has_ext(env, RVU) ? PRV_U : PRV_M); in helper_mret()
351 if ((env->priv_ver >= PRIV_VERSION_1_12_0) && (prev_priv != PRV_M)) { in helper_mret()
399 } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) { in helper_wrs_nto()
433 if (env->priv == PRV_M || in helper_hyp_tlb_flush()
454 if (env->priv == PRV_M) { in check_access_hlsv()
H A Dpmp.c266 if (mode == PRV_M && !(privs & PMP_EXEC)) { in pmp_hart_has_privs_default()
277 if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) { in pmp_hart_has_privs_default()
376 if ((mode != PRV_M) || pmp_is_locked(env, i)) { in pmp_hart_has_privs()
383 if (mode == PRV_M) { in pmp_hart_has_privs()
H A Dcpu_helper.c50 if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) { in riscv_env_mmu_index()
53 (mode != PRV_M); in riscv_env_mmu_index()
86 case PRV_M: in cpu_get_fcfien()
115 case PRV_M: /* M-mode shadow stack is always off */ in cpu_get_bcfien()
236 case PRV_M: in riscv_cpu_update_mask()
515 mie = (env->priv < PRV_M) || in riscv_cpu_local_irq_pending()
516 (env->priv == PRV_M && get_field(env->mstatus, MSTATUS_MIE)); in riscv_cpu_local_irq_pending()
768 if (priv <= PRV_M) { in riscv_cpu_set_aia_ireg_rmw_fn()
776 g_assert(newpriv <= PRV_M && newpriv != PRV_RESERVED); in riscv_cpu_set_mode()
915 if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { in get_physical_address()
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H A Dpmu.c112 if ((env->priv == PRV_M && in riscv_pmu_incr_ctr_rv32()
153 if ((env->priv == PRV_M && in riscv_pmu_incr_ctr_rv64()
H A Dcsr.c50 if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { in smstateen_acc_ok()
142 if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) { in ctr()
405 if (env->priv < PRV_M) { in hstateen_pred()
442 if (env->priv < PRV_M) { in sstateen()
478 if (env->priv == PRV_M) { in sstc()
622 if (env->priv == PRV_M) { in seed()
1078 curr_val += counter_arr[PRV_M]; in riscv_pmu_ctr_get_fixed_counters_val()
1577 case PRV_M: in legalize_mpp()
2069 priv = PRV_M; in rmw_xireg()
2099 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); in rmw_xireg()
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H A Dcpu.h661 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { in cpu_address_mode()
678 case PRV_M: in cpu_get_xl()
H A Dcpu_bits.h624 #define PRV_M 3 macro
H A Dcpu.c943 env->priv = PRV_M; in riscv_cpu_reset_hold()
/openbmc/qemu/hw/intc/
H A Driscv_imsic.c213 if (priv == PRV_M && !virt) { in riscv_imsic_rmw()
384 riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, in riscv_imsic_realize()
/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h67 #define PRV_M 3 macro