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Searched refs:MDIO_DEVAD_NONE (Results 1 – 25 of 72) sorted by relevance

123

/openbmc/u-boot/drivers/net/phy/
H A Dmarvell.c108 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
111 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
112 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
121 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
123 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
124 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
134 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
[all …]
H A Dmscc.c276 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, in vsc8584_csr_write()
278 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, in vsc8584_csr_write()
280 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in vsc8584_csr_write()
289 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
292 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_cmd()
297 reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, in vsc8584_cmd()
303 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
319 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
331 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, in vsc8584_micro_deassert_reset()
339 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
[all …]
H A Dvitesse.c74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
77 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
90 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
126 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
132 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
136 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
150 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL); in vsc8601_add_skew()
155 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
175 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
178 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19); in vsc8574_config()
[all …]
H A Dmeson-gxl.c43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); in meson_gxl_startup()
62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
70 exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION); in meson_gxl_startup()
103 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_phy_config()
[all …]
H A Datheros.c22 phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
24 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
42 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
44 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); in ar8035_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_config()
62 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_config()
[all …]
H A Drealtek.c64 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extread()
68 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); in rtl8211f_phy_extread()
69 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in rtl8211f_phy_extread()
70 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); in rtl8211f_phy_extread()
78 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, in rtl8211f_phy_extwrite()
81 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); in rtl8211f_phy_extwrite()
82 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in rtl8211f_phy_extwrite()
83 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); in rtl8211f_phy_extwrite()
109 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
[all …]
H A Dbroadcom.c41 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
44 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
46 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
49 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
64 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5461_config()
66 reg18 = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm5461_config()
72 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg18); in bcm5461_config()
78 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, in bcm5461_config()
80 reg1c = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD); in bcm5461_config()
[all …]
H A Dmicrel_ksz90x1.c49 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
217 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
219 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
226 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); in ksz9021_phy_extended_read()
227 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); in ksz9021_phy_extended_read()
265 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
290 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
293 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
296 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
299 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
[all …]
H A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
24 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
27 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
29 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
68 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); in dp83865_parse_status()
121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
H A Dphy.c46 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
72 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); in genphy_config_advert()
79 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
91 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
110 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
140 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
153 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
163 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
193 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
228 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
[all …]
H A Det1011c.c30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
59 phy_write(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG, in et1011c_parse_status()
H A Dmicrel_ksz8xxx.c33 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
37 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, in ksz_genconfig_bcastoff()
66 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
68 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); in ksz8051_config()
109 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, in ksz8895_write_smireg()
117 MDIO_DEVAD_NONE, smireg_to_reg(smireg));
H A Ddavicom.c29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
31 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
34 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
H A Dti.c305 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); in dp83867_config()
306 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, in dp83867_config()
319 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
337 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL); in dp83867_config()
340 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
345 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, in dp83867_config()
355 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2); in dp83867_config()
360 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
366 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); in dp83867_config()
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c94 return t3_phy_reset(cphy, MDIO_DEVAD_NONE, 0); in vsc8211_reset()
99 return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE, in vsc8211_intr_enable()
105 return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE, 0); in vsc8211_intr_disable()
113 return t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &val); in vsc8211_intr_clear()
118 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR, in vsc8211_autoneg_enable()
125 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR, in vsc8211_autoneg_restart()
136 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr); in vsc8211_get_link_status()
138 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, &status); in vsc8211_get_link_status()
148 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, in vsc8211_get_link_status()
163 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_AUX_CTRL_STAT, in vsc8211_get_link_status()
[all …]
/openbmc/u-boot/board/spear/x600/
H A Dx600.c76 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
77 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
83 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
110 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
123 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
126 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
129 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c60 if (dev_addr == MDIO_DEVAD_NONE) { in pfe_phy_read()
71 if (dev_addr == MDIO_DEVAD_NONE) in pfe_phy_read()
115 if (dev_addr == MDIO_DEVAD_NONE) { in pfe_phy_write()
126 if (dev_addr == MDIO_DEVAD_NONE) in pfe_phy_write()
169 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0); in pfe_configure_serdes()
170 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1); in pfe_configure_serdes()
171 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2); in pfe_configure_serdes()
172 pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3); in pfe_configure_serdes()
175 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000); in pfe_configure_serdes()
184 pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value); in pfe_configure_serdes()
[all …]
/openbmc/u-boot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c95 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
102 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4); in board_phy_config()
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
107 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
111 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG); in board_phy_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()
/openbmc/u-boot/board/compulab/cl-som-imx7/
H A Dcl-som-imx7.c135 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in cl_som_imx7_rgmii_rework()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in cl_som_imx7_rgmii_rework()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in cl_som_imx7_rgmii_rework()
138 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in cl_som_imx7_rgmii_rework()
144 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in cl_som_imx7_rgmii_rework()
145 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in cl_som_imx7_rgmii_rework()
147 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
150 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
[all …]
/openbmc/u-boot/board/congatec/cgtqmx6eval/
H A Dcgtqmx6eval.c282 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_eth_init()
283 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_eth_init()
331 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in mx6_rgmii_rework()
332 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in mx6_rgmii_rework()
336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); in mx6_rgmii_rework()
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); in mx6_rgmii_rework()
[all …]
/openbmc/u-boot/board/gdsys/a38x/
H A Dihs_phys.c32 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004); in ihs_phy_config()
33 reg = phy_read(phydev, MDIO_DEVAD_NONE, 16); in ihs_phy_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, 16, reg); in ihs_phy_config()
41 reg = phy_read(phydev, MDIO_DEVAD_NONE, 26); in ihs_phy_config()
47 phy_write(phydev, MDIO_DEVAD_NONE, 26, reg); in ihs_phy_config()
50 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in ihs_phy_config()
51 reg = phy_read(phydev, MDIO_DEVAD_NONE, 4); in ihs_phy_config()
53 phy_write(phydev, MDIO_DEVAD_NONE, 4, reg); in ihs_phy_config()
54 reg = phy_read(phydev, MDIO_DEVAD_NONE, 9); in ihs_phy_config()
56 phy_write(phydev, MDIO_DEVAD_NONE, 9, reg); in ihs_phy_config()
[all …]
/openbmc/u-boot/board/k+p/kp_imx6q_tpc/
H A Dkp_imx6q_tpc.c140 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8031_phy_fixup()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8031_phy_fixup()
142 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8031_phy_fixup()
144 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8031_phy_fixup()
147 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8031_phy_fixup()
150 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8031_phy_fixup()
151 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8031_phy_fixup()
153 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8031_phy_fixup()
/openbmc/u-boot/board/logicpd/imx6/
H A Dimx6logic.c98 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in ar8031_phy_fixup()
99 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8031_phy_fixup()
100 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8031_phy_fixup()
102 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8031_phy_fixup()
105 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in ar8031_phy_fixup()
108 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in ar8031_phy_fixup()
109 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8031_phy_fixup()
111 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in ar8031_phy_fixup()
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dimx8mq_evk.c96 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in board_phy_config()
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); in board_phy_config()
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in board_phy_config()
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in board_phy_config()
/openbmc/u-boot/board/technexion/pico-imx7d/
H A Dpico-imx7d.c200 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in board_phy_config()
201 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in board_phy_config()
202 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in board_phy_config()
204 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in board_phy_config()
207 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in board_phy_config()
210 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in board_phy_config()
211 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in board_phy_config()
213 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); in board_phy_config()

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