Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10 |
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d4e3d798 |
| 01-Apr-2022 |
Dylan Hung <dylan_hung@aspeedtech.com> |
net: phy: realtek: Add RTL8211F-VD driver support
RTL8211F(D)-VD-CG is basically the same with typical RTL8211F, except the PHY ID is 0x1cc870 or 0x1cc878.
Signed-off-by: Dylan Hung <dylan_hung@asp
net: phy: realtek: Add RTL8211F-VD driver support
RTL8211F(D)-VD-CG is basically the same with typical RTL8211F, except the PHY ID is 0x1cc870 or 0x1cc878.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Change-Id: I91acd1ad11a32586476b271c5298146cba5c365c
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Revision tags: v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01 |
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9e93b9a9 |
| 07-Jul-2021 |
Dylan Hung <dylan_hung@aspeedtech.com> |
net: phy: realtek: Add RTL8211FD_VX driver support
RTL8211FD-VX is basically the same with typical RTL8211F, except: 1. the PHY ID is 0x1cc859 2. 10M/100M is disabled by default, and needs for a pat
net: phy: realtek: Add RTL8211FD_VX driver support
RTL8211FD-VX is basically the same with typical RTL8211F, except: 1. the PHY ID is 0x1cc859 2. 10M/100M is disabled by default, and needs for a patch (TBD)
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Change-Id: I1092b51c9e3a4a5a41246560128e37d825124bfd
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Revision tags: v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13 |
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7643081d |
| 03-May-2020 |
Fugang Duan <fugang.duan@nxp.com> |
net: phy: realtek: add rx delay support for RTL8211F
Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by:
net: phy: realtek: add rx delay support for RTL8211F
Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: If7ab581532c6a53c336e9f86da0b166aa1ee4b32
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Revision tags: v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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68489ed0 |
| 24-Jan-2019 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-net
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e57c9fdb |
| 16-Jan-2019 |
Carlo Caione <ccaione@baylibre.com> |
net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Wri
net: phy: realtek: Add functions to read PHY's extended registers
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Write the target Register Data 3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE Standard Registers)
Hook the missing functions so that we can use the `mdio rx/wx` command to easily access the extended registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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a57d45db |
| 26-Jul-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-net
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05b60ac5 |
| 25-Jul-2018 |
Joe Hershberger <joe.hershberger@ni.com> |
net: phy: Clean up includes of common.h
We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first.
Also, common.h includ
net: phy: Clean up includes of common.h
We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first.
Also, common.h includes config.h as the first thing it does, so don't include it directly.
Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series.
[1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
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Revision tags: v2018.07 |
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83d290c5 |
| 06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
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b0af1044 |
| 22-Mar-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-net
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Revision tags: v2018.03 |
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66526e70 |
| 14-Feb-2018 |
kevans@FreeBSD.org <kevans@FreeBSD.org> |
net: phy: Add PHY_RTL8211E_PINE64_GIGABIT_FIX for realtek phys
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off on the PHY, as well as flipping some magical undocumented bits
net: phy: Add PHY_RTL8211E_PINE64_GIGABIT_FIX for realtek phys
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off on the PHY, as well as flipping some magical undocumented bits. The magic number comes from the Pine64 engineering team, presumably as a proxy from Realtek. This configuration fixes the throughput on some Pine64 models. Packet loss of up to 60-70% has been observed without this.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Revision tags: v2018.01, v2017.11 |
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ec6bc928 |
| 07-Sep-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-net
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05b29aa0 |
| 18-Aug-2017 |
Madalin Bucur <madalin.bucur@nxp.com> |
net: phy: realtek: fix enabling of the TX-delay for RTL8211F
The old logic always enabled the TX-delay when the phy-mode was set to PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay f
net: phy: realtek: fix enabling of the TX-delay for RTL8211F
The old logic always enabled the TX-delay when the phy-mode was set to PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and disable it for PHY_INTERFACE_MODE_RGMII.
Based on a similar change made in the Linux Realtek PHY driver by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: York Sun <york.sun@nxp.com>
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f2465934 |
| 16-Dec-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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cebf3f55 |
| 08-Nov-2016 |
oliver@schinagl.nl <oliver@schinagl.nl> |
net: phy: realtek: Only force master mode on rtl8211b/c
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY") added the define to force the PHY into master mode. Unfortunatly this
net: phy: realtek: Only force master mode on rtl8211b/c
Commit 525d187af ("net: phy: Optionally force master mode for RTL PHY") added the define to force the PHY into master mode. Unfortunatly this is an all or nothing switch. So it applies to either all PHY's or no PHY's.
The bug that define tried to solve was a buggy PLL in the RTL8211C only.
The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was replaced with an RTL8211E. With this define however, both lime2 boards are either forced to master mode or not. We could of course have a binary for each board, but the following patch fixes this by adding a 'quirk' to the flags to the rtl8211b and rtl8211c only. It is now possible to force master mode, but only have it apply to the rtl8211b and rtl8211c.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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cbe40e11 |
| 08-Nov-2016 |
oliver@schinagl.nl <oliver@schinagl.nl> |
net: phy: realtek: make define more consistent
All internal defines in the realtek phy are with a small X, except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Sc
net: phy: realtek: make define more consistent
All internal defines in the realtek phy are with a small X, except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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020f6762 |
| 08-Nov-2016 |
oliver@schinagl.nl <oliver@schinagl.nl> |
net: phy: realtek: Use the BIT() macro
The BIT macro is the preferred method to set bits. This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <oliver@schinag
net: phy: realtek: Use the BIT() macro
The BIT macro is the preferred method to set bits. This patch adds the bit macro and converts bit invocations.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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Revision tags: v2016.07, openbmc-20160624-1 |
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dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
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ec8fb48c |
| 24-May-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
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b733c278 |
| 18-May-2016 |
Michal Simek <michal.simek@xilinx.com> |
net: phy: Handle phy_startup() error codes properly
Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <
net: phy: Handle phy_startup() error codes properly
Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
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563d8d93 |
| 21-Mar-2016 |
Karsten Merker <merker@debian.org> |
net: phy: Realtek RTL8211B/C PHY ID fix
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.
The lowest four bits of t
net: phy: Realtek RTL8211B/C PHY ID fix
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.
The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision.
After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C.
Fix this by setting the full PHY ID in the RTL8211B_driver uid field.
Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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40345e9e |
| 01-Apr-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of http://git.denx.de/u-boot-sunxi
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525d187a |
| 25-Mar-2016 |
Michael Haas <haas@computerlinguist.org> |
net: phy: Optionally force master mode for RTL PHY
This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T m
net: phy: Optionally force master mode for RTL PHY
This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode.
This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2.
There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef.
CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com
Signed-off-by: Michael Haas <haas@computerlinguist.org> Tested-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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6a10bc5b |
| 13-Feb-2016 |
Michal Simek <monstr@monstr.eu> |
net: phy: realtek: Use generic genphy_parse_link() for RTL8211E
The problem with current implementation is that SPDDONE bit is 1 but link bit is zero. That's why phydev->link is setup to 0 which end
net: phy: realtek: Use generic genphy_parse_link() for RTL8211E
The problem with current implementation is that SPDDONE bit is 1 but link bit is zero. That's why phydev->link is setup to 0 which ending up in driver failure that link is not up.
Log: Zynq> dhcp ethernet@e000b000 Waiting for PHY auto negotiation to complete....... done ethernet@e000b000: No link.
There is at least 1ms delay between spddone bit and link up.
Use genphy_read_status() instead of realtek implemenation which is working with page 11. Linux driver is also using generic implementation.
Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Revision tags: v2016.01-rc1, v2015.10, v2015.10-rc5, v2015.10-rc4, v2015.10-rc3, v2015.10-rc2 |
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fcd78fa6 |
| 12-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-net
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Revision tags: v2015.10-rc1, v2015.07, v2015.07-rc3, v2015.07-rc2 |
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90712741 |
| 21-May-2015 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/phy: set led for rtl8211f phy
Initialize LCR rigister to configure green LED for Link, yellow LED for Active.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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