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Searched refs:M4 (Results 1 – 25 of 80) sorted by relevance

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/openbmc/u-boot/board/htkw/mcx/
H A Dmcx.h77 MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
78 MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
79 MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
80 MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
81 MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
82 MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
83 MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
84 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
85 MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
86 MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
[all …]
/openbmc/u-boot/board/overo/
H A Dovero.h44 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
46 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
48 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
79 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
83 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
86 MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
87 MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
88 MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
89 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
91 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
[all …]
H A Dcommon.c109 MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
137 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
138 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
139 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
157 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
166 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
172 MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
185 MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
203 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
205 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
[all …]
/openbmc/u-boot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h115 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
116 MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
117 MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
119 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
121 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
128 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
130 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
131 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
132 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
134 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
[all …]
/openbmc/u-boot/board/pandora/
H A Dpandora.h131 MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
132 MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\
133 MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
134 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
135 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\
136 MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\
137 MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\
138 MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
139 MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
140 MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\
[all …]
/openbmc/u-boot/board/corscience/tricorder/
H A Dtricorder.h77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
148 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
162 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
185 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
186 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
187 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
188 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
189 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
190 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
[all …]
/openbmc/u-boot/board/lg/sniper/
H A Dsniper.h53 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \
54 MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \
55 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \
56 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\
57 MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\
58 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\
59 MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\
60 MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\
61 MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\
62 MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\
[all …]
/openbmc/u-boot/board/ti/panda/
H A Dpanda_mux_data.h49 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
50 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
51 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
52 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
53 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
54 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
55 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
56 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
57 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
58 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
[all …]
/openbmc/u-boot/board/technexion/twister/
H A Dtwister.h121 MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
124 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
133 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
134 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
135 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
170 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
184 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
197 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
199 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
200 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
[all …]
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h157 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
171 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
194 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
195 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
196 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
197 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
198 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
199 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
200 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
201 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
[all …]
/openbmc/u-boot/board/timll/devkit8000/
H A Ddevkit8000.h151 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
165 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
188 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
189 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
190 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
191 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
192 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
193 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
194 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
195 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
[all …]
/openbmc/u-boot/board/8dtech/eco5pk/
H A Deco5pk.h112 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
122 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
130 MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
131 MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
132 MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
133 MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
134 MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
135 MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
136 MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
137 MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
[all …]
/openbmc/u-boot/board/nokia/rx51/
H A Drx51.h153 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
167 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
190 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
191 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
192 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
193 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
194 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
195 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
196 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
197 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
[all …]
/openbmc/u-boot/board/compulab/cm_t3517/
H A Dmux.c88 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ in set_muxconf_regs()
90 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ in set_muxconf_regs()
93 MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ in set_muxconf_regs()
99 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ in set_muxconf_regs()
103 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ in set_muxconf_regs()
109 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ in set_muxconf_regs()
111 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ in set_muxconf_regs()
114 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ in set_muxconf_regs()
116 MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ in set_muxconf_regs()
118 MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ in set_muxconf_regs()
[all …]
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero_mux_data.h99 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
100 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
101 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
102 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
103 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
104 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
105 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
106 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
107 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
108 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/flex/
H A Dflex_2.6.4.bb36 M4 = "${bindir}/m4"
37 M4:class-native = "${STAGING_BINDIR_NATIVE}/m4"
38 EXTRA_OECONF += "ac_cv_path_M4=${M4} ac_cv_func_reallocarray=no"
44 create_wrapper ${D}/${bindir}/flex M4=${M4}
48 create_wrapper ${D}/${bindir}/flex M4=${M4}
/openbmc/u-boot/board/quipos/cairo/
H A Dcairo.h36 MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
37 MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
39 MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
40 MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
45 MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
47 MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
48 MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
49 MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
50 MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
51 MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
[all …]
/openbmc/u-boot/board/isee/igep00x0/
H A Digep00x0.h114 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
115 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
116 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
117 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
118 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
119 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
120 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
121 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
122 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
123 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
[all …]
/openbmc/u-boot/board/technexion/tao3530/
H A Dtao3530.h148 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \
163 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \
192 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
193 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
194 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \
195 MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
200 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
202 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \
217 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \
222 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
[all …]
/openbmc/u-boot/board/freescale/lx2160a/
H A DREADME88 1 |Mezzanine:X-M4-PCIE-SGMII (29733)
91 |Mezzanine:X-M4-PCIE-SGMII (29733)
98 |Mezzanine:X-M4-PCIE-SGMII (29733)
105 |Mezzanine:X-M4-PCIE-SGMII (29733)
126 |Mezzanine:X-M4-PCIE-SGMII (29733)
133 |Mezzanine:X-M4-PCIE-SGMII (29733)
160 3 |Mezzanine:X-M4-PCIE-SGMII (29733)
163 |Mezzanine:X-M4-PCIE-SGMII (29733)
167 5 |Mezzanine:X-M4-PCIE-SGMII (29733)
174 11 |Mezzanine:X-M4-PCIE-SGMII (29733)
[all …]
/openbmc/u-boot/board/logicpd/am3517evm/
H A Dam3517evm.h125 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
162 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
177 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
191 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
192 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\
193 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
194 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
221 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
223 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
225 MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
[all …]
/openbmc/u-boot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h40 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
41 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
42 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
43 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
/openbmc/u-boot/board/ti/am3517crane/
H A Dam3517crane.h83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
89 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
109 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
126 MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
224 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
225 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm4.inc2 # Tune Settings for Cortex-M4
6 TUNEVALID[cortexm4] = "Enable Cortex-M4 specific processor optimizations"
/openbmc/u-boot/board/ti/evm/
H A Devm.h131 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
168 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
183 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
230 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
232 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
234 MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
236 MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
276 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
278 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
297 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
[all …]

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