Lines Matching refs:M4

112 	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | DIS  | M4)) \
122 	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) \
130 	MUX_VAL(CP(DSS_DATA0),		(IEN  | PTD | DIS | M4)) \
131 	MUX_VAL(CP(DSS_DATA1),		(IEN  | PTD | DIS | M4)) \
132 	MUX_VAL(CP(DSS_DATA2),		(IEN  | PTD | DIS | M4)) \
133 	MUX_VAL(CP(DSS_DATA3),		(IEN  | PTD | DIS | M4)) \
134 	MUX_VAL(CP(DSS_DATA4),		(IEN  | PTD | DIS | M4)) \
135 	MUX_VAL(CP(DSS_DATA5),		(IEN  | PTD | DIS | M4)) \
136 	MUX_VAL(CP(DSS_DATA6),		(IEN  | PTD | DIS | M4)) \
137 	MUX_VAL(CP(DSS_DATA7),		(IEN  | PTD | DIS | M4)) \
138 	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTU | EN  | M4)) \
139 	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTU | EN  | M4)) \
140 	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTU | EN  | M4)) \
141 	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTU | EN  | M4)) \
142 	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTU | EN  | M4)) \
143 	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | EN  | M4)) \
144 	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | EN  | M4)) \
145 	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTU | EN  | M4)) \
146 	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTU | EN  | M4)) \
147 	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | EN  | M4)) \
159 	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
174 	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
187 	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
188 	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
189 	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
190 	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
215 	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M4)) /* LED ACT */ \
219 	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
221 	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
223 	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
225 	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
256 	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
257 	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
264 	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
266 	MUX_VAL(CP(MCSPI2_CS1),		(IDIS | PTD | EN  | M4)) \
316 	MUX_VAL(CP(SYS_NRESWARM),	(IDIS | PTU | DIS | M4)) \
318 	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /* GPIO_2 */\
320 	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /* GPIO_3 */\
321 	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /* GPIO_4 */\
322 	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /* GPIO_5 */\
323 	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /* GPIO_6 */\
324 	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /* GPIO_7 */\
325 	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /* GPIO_8 */\