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Searched refs:M3 (Results 1 – 25 of 111) sorted by relevance

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/openbmc/u-boot/board/ti/dra7xx/
H A Dmux_data.h15 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
16 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
17 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
18 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
19 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
20 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
21 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
22 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
23 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
24 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
[all …]
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero_mux_data.h56 {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */
57 {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */
58 {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */
59 {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */
60 {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */
61 {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */
62 {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */
63 {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */
64 {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */
65 {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */
[all …]
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dmux.c89 {VIN2A_D10, (M3 | PIN_OUTPUT_PULLUP) }, /* VIN2A_D10.MDIO_MCLK */
90 {VIN2A_D11, (M3 | PIN_INPUT_PULLUP) }, /* VIN2A_D11.MDIO_D */
92 {VIN2A_D12, (M3 | PIN_OUTPUT) }, /* VIN2A_D12.RGMII1_TXC */
93 {VIN2A_D13, (M3 | PIN_OUTPUT) }, /* VIN2A_D13.RGMII1_TXCTL */
94 {VIN2A_D14, (M3 | PIN_OUTPUT) }, /* VIN2A_D14.RGMII1_TXD3 */
95 {VIN2A_D15, (M3 | PIN_OUTPUT) }, /* VIN2A_D15.RGMII1_TXD2 */
96 {VIN2A_D16, (M3 | PIN_OUTPUT) }, /* VIN2A_D16.RGMII1_TXD1 */
97 {VIN2A_D17, (M3 | PIN_OUTPUT) }, /* VIN2A_D17.RGMII1_TXD0 */
98 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D18.RGMII1_RXC */
99 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN) }, /* VIN2A_D19.RGMII1_RXCTL */
[all …]
/openbmc/u-boot/board/compulab/cm_t35/
H A Dcm_t35.c254 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in cm_t3x_set_common_muxconf()
255 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in cm_t3x_set_common_muxconf()
256 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in cm_t3x_set_common_muxconf()
257 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in cm_t3x_set_common_muxconf()
258 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in cm_t3x_set_common_muxconf()
259 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in cm_t3x_set_common_muxconf()
260 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in cm_t3x_set_common_muxconf()
261 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in cm_t3x_set_common_muxconf()
262 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in cm_t3x_set_common_muxconf()
263 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in cm_t3x_set_common_muxconf()
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dtraps_64.c1096 #define M3 145 macro
1100 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1105 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1106 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1107 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1109 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1110 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1111 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1112 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1113 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
[all …]
/openbmc/u-boot/board/compulab/cm_t3517/
H A Dmux.c202 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in set_muxconf_regs()
203 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in set_muxconf_regs()
204 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in set_muxconf_regs()
205 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in set_muxconf_regs()
206 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in set_muxconf_regs()
207 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in set_muxconf_regs()
208 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in set_muxconf_regs()
209 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in set_muxconf_regs()
210 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in set_muxconf_regs()
211 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in set_muxconf_regs()
[all …]
/openbmc/u-boot/board/ti/am57xx/
H A Dmux_data.h103 {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
104 {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
105 {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
106 {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
107 {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
108 {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
109 {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
110 {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
111 {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
112 {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
[all …]
/openbmc/u-boot/board/quipos/cairo/
H A Dcairo.h84 MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
85 MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
86 MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
87 MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
88 MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
89 MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
90 MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
91 MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
92 MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
93 MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
[all …]
/openbmc/u-boot/board/amazon/kc1/
H A Dkc1.h31 { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */
81 { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
82 { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
85 { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
86 { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
87 { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
88 { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
/openbmc/u-boot/board/ti/panda/
H A Dpanda.c81 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); in get_board_revision()
82 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); in get_board_revision()
93 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
95 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
97 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
111 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
146 writew((IEN | M3), in is_panda_es_rev_b3()
H A Dpanda_mux_data.h65 {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
66 {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
67 {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
82 {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
/openbmc/u-boot/board/ti/beagle/
H A Dbeagle.h262 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
263 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
264 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
265 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
266 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
267 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
268 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
269 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
270 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
271 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
[all …]
/openbmc/u-boot/board/nokia/rx51/
H A Drx51.h258 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
259 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
260 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
261 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
262 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
263 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
264 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
265 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
266 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
267 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dwkup_m3_rproc.txt1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
/openbmc/u-boot/board/htkw/mcx/
H A Dmcx.h264 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
266 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
268 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
270 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
272 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
348 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
350 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
352 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
353 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
354 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7m/
H A Dtune-cortexm3.inc2 # Tune Settings for Cortex-M3
6 TUNEVALID[cortexm3] = "Enable Cortex-M3 specific processor optimizations"
/openbmc/qemu/docs/system/arm/
H A Dstellaris.rst7 - Cortex-M3 CPU core.
19 - Cortex-M3 CPU core.
H A Dstm32.rst9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
32 * ARM Cortex-M3, Cortex M4F
/openbmc/u-boot/board/overo/
H A Dcommon.c211 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
212 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
213 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
214 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
215 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
216 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
232 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
233 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
234 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
235 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
[all …]
/openbmc/u-boot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h120 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
348 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
350 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
352 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
353 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
354 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
355 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
356 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
357 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
358 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
[all …]
/openbmc/u-boot/board/ti/am3517crane/
H A Dam3517crane.h293 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
294 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
295 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
296 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
297 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
298 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
299 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
300 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
301 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
302 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
[all …]
/openbmc/linux/drivers/soc/renesas/
H A DKconfig219 bool "ARM64 Platform support for R-Car M3-N"
223 This enables support for the Renesas R-Car M3-N SoC.
227 bool "ARM64 Platform support for R-Car M3-W"
231 This enables support for the Renesas R-Car M3-W SoC.
234 bool "ARM64 Platform support for R-Car M3-W+"
238 This enables support for the Renesas R-Car M3-W+ SoC.
391 bool "System Controller support for R-Car M3-N" if COMPILE_TEST
395 bool "System Controller support for R-Car M3-W" if COMPILE_TEST
399 bool "System Controller support for R-Car M3-W+" if COMPILE_TEST
/openbmc/u-boot/board/technexion/twister/
H A Dtwister.h123 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
346 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
348 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
350 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
351 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
352 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
353 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
354 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
355 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
356 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
[all …]
/openbmc/linux/drivers/soc/ti/
H A DKconfig44 tristate "TI AMx3 Wkup-M3 IPC Driver"
48 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
50 to communicate and use the Wakeup M3 for PM features like suspend
/openbmc/linux/arch/arm64/crypto/
H A Dpolyval-ce-core.S41 M3 .req v3 label
223 ld1 {M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
246 karatsuba1 M3 KEY5
278 ld1 {M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
283 karatsuba1 M3 KEY5

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