/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | marvell,gicp.txt | 4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI 7 into GIC SPI interrupts. 15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
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H A D | ti,omap4-wugen-mpu | 4 routes interrupts to the GIC, and also serves as a wakeup source. It 18 - Because this HW ultimately routes interrupts to the GIC, the 19 interrupt specifier must be that of the GIC.
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H A D | nvidia,tegra20-ictlr.txt | 4 interrupts to the GIC, and also serves as a wakeup source. It is also 25 - Because this HW ultimately routes interrupts to the GIC, the 26 interrupt specifier must be that of the GIC.
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H A D | marvell,icu.txt | 6 communicating them to the GIC in the AP, the unit translates interrupt 7 requests on input wires to MSG memory mapped transactions to the GIC. 8 These messages will access a different GIC memory area depending on 39 - msi-parent: Should point to the GICP controller, the GIC extension
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H A D | marvell,armada-8k-pic.txt | 6 typically connected to the GIC as the primary interrupt controller. 15 typically the GIC
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H A D | marvell,odmi-controller.txt | 23 - marvell,spi-base : List of GIC base SPI interrupts, one for each 27 for details about the GIC Device Tree binding.
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H A D | marvell,armada-370-xp-mpic.txt | 24 connected as a slave to the Cortex-A9 GIC. The provided interrupt 25 indicate to which GIC interrupt the MPIC output is connected.
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H A D | mediatek,sysirq.txt | 3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI 30 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
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H A D | fsl,ls-scfg-msi.txt | 17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-platform-devices-ampere-smpro | 65 …| GIC (other) | 5 | 0 | ERR0 | 0 … 67 …| GIC (other) | 5 | 1 | ERR1 | 0 … 69 …| GIC (other) | 5 | 2 | ERR2 | 0 … 71 …| GIC (other) | 5 | 3 | ERR3 | 0 … 73 …| GIC (other) | 5 | 4 | ERR4 | 0 … 75 …| GIC (other) | 5 | 5 | ERR5 | 0 … 77 …| GIC (other) | 5 | 6 | ERR6 | 0 … 79 …| GIC (other) | 5 | 7 | ERR7 | 0 … 81 …| GIC (other) | 5 | 8 | ERR8 | 0 … 83 …| GIC (other) | 5 | 9 | ERR9 | 0 … [all …]
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/openbmc/qemu/docs/system/arm/ |
H A D | sbsa.rst | 24 - GIC version 3 63 - GIC addresses 85 GIC information is present in devicetree. 88 GIC ITS information is present in devicetree.
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H A D | xlnx-zynq.rst | 13 - GIC v1
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/openbmc/linux/drivers/net/ethernet/renesas/ |
H A D | ravb_ptp.c | 195 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts() 251 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout() 263 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout() 304 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt() 347 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
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/openbmc/linux/arch/mips/boot/dts/mti/ |
H A D | sead3.dts | 64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */ 227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */ 242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */ 253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
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/openbmc/linux/Documentation/virt/kvm/devices/ |
H A D | arm-vgic.rst | 27 Base address in the guest physical address space of the GIC distributor 32 Base address in the guest physical address space of the GIC virtual cpu 110 a GIC without the security extensions expose group 0 and group 1 active 132 this GIC instance, ranging from 64 to 1024, in increments of 32. 138 -EBUSY Value has already be set, or GIC has already been initialized
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H A D | vcpu.rst | 51 -ENODEV PMUv3 not supported or GIC not initialized 58 virtual GIC implementation, this must be done after initializing the in-kernel 70 -ENODEV PMUv3 not supported or GIC not initialized 120 -ENODEV PMUv3 not supported or GIC not initialized 159 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
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/openbmc/linux/Documentation/devicetree/bindings/arm/freescale/ |
H A D | fsl,vf610-mscm-ir.txt | 19 Flags get passed only when using GIC as parent. Flags 20 encoding as documented by the GIC bindings.
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/openbmc/u-boot/arch/arm/cpu/armv7/ |
H A D | nonsec_virt.S | 125 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset 131 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 132 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7
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/openbmc/qemu/qapi/ |
H A D | misc-target.json | 299 # The struct describes capability for a specific GIC (Generic 304 # @version: version of GIC to be described. Currently, only 2 and 3 307 # @emulated: whether current QEMU/hardware supports emulated GIC 311 # GIC device in kernel.
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | arm-realview-eb.dts | 34 * This is the core tile with the CPU and GIC etc for the 64 * to the GIC on the core tile.
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H A D | arm-realview-eb-mp.dtsi | 119 * to the GIC on the core tile. 181 * GIC.
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/openbmc/linux/Documentation/devicetree/bindings/misc/ |
H A D | fsl,qoriq-mc.txt | 38 For GICv3 and GIC ITS bindings, see: 127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier 134 associated with the listed GIC ITS, with the msi-specifier
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/openbmc/linux/Documentation/devicetree/bindings/arm/omap/ |
H A D | mpu.txt | 5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/ |
H A D | 0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch | 36 + * Disable GIC CPU interface to prevent pending interrupt
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/openbmc/linux/arch/arm64/boot/dts/apm/ |
H A D | apm-shadowcat.dtsi | 126 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 128 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ 129 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ 130 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ 131 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
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