xref: /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt (revision c25141062a82ae8bddced1b3ce2b57a1c0efabe0)
1*11f69da0SThomas PetazzoniMarvell GICP Controller
2*11f69da0SThomas Petazzoni-----------------------
3*11f69da0SThomas Petazzoni
4*11f69da0SThomas PetazzoniGICP is a Marvell extension of the GIC that allows to trigger GIC SPI
5*11f69da0SThomas Petazzoniinterrupts by doing a memory transaction. It is used by the ICU
6*11f69da0SThomas Petazzonilocated in the Marvell CP110 to turn wired interrupts inside the CP
7*11f69da0SThomas Petazzoniinto GIC SPI interrupts.
8*11f69da0SThomas Petazzoni
9*11f69da0SThomas PetazzoniRequired properties:
10*11f69da0SThomas Petazzoni
11*11f69da0SThomas Petazzoni- compatible: Must be "marvell,ap806-gicp"
12*11f69da0SThomas Petazzoni
13*11f69da0SThomas Petazzoni- reg: Must be the address and size of the GICP SPI registers
14*11f69da0SThomas Petazzoni
15*11f69da0SThomas Petazzoni- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
16*11f69da0SThomas Petazzoni  for this GICP
17*11f69da0SThomas Petazzoni
18*11f69da0SThomas Petazzoni- msi-controller: indicates that this is an MSI controller
19*11f69da0SThomas Petazzoni
20*11f69da0SThomas PetazzoniExample:
21*11f69da0SThomas Petazzoni
22*11f69da0SThomas Petazzonigicp_spi: gicp-spi@3f0040 {
23*11f69da0SThomas Petazzoni	compatible = "marvell,ap806-gicp";
24*11f69da0SThomas Petazzoni	reg = <0x3f0040 0x10>;
25*11f69da0SThomas Petazzoni	marvell,spi-ranges = <64 64>, <288 64>;
26*11f69da0SThomas Petazzoni	msi-controller;
27*11f69da0SThomas Petazzoni};
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