1*33a6c324SThomas PetazzoniMarvell Armada 7K/8K PIC Interrupt controller 2*33a6c324SThomas Petazzoni--------------------------------------------- 3*33a6c324SThomas Petazzoni 4*33a6c324SThomas PetazzoniThis is the Device Tree binding for the PIC, a secondary interrupt 5*33a6c324SThomas Petazzonicontroller available on the Marvell Armada 7K/8K ARM64 SoCs, and 6*33a6c324SThomas Petazzonitypically connected to the GIC as the primary interrupt controller. 7*33a6c324SThomas Petazzoni 8*33a6c324SThomas PetazzoniRequired properties: 9*33a6c324SThomas Petazzoni- compatible: should be "marvell,armada-8k-pic" 10*33a6c324SThomas Petazzoni- interrupt-controller: identifies the node as an interrupt controller 11*33a6c324SThomas Petazzoni- #interrupt-cells: the number of cells to define interrupts on this 12*33a6c324SThomas Petazzoni controller. Should be 1 13*33a6c324SThomas Petazzoni- reg: the register area for the PIC interrupt controller 14*33a6c324SThomas Petazzoni- interrupts: the interrupt to the primary interrupt controller, 15*33a6c324SThomas Petazzoni typically the GIC 16*33a6c324SThomas Petazzoni 17*33a6c324SThomas PetazzoniExample: 18*33a6c324SThomas Petazzoni 19*33a6c324SThomas Petazzoni pic: interrupt-controller@3f0100 { 20*33a6c324SThomas Petazzoni compatible = "marvell,armada-8k-pic"; 21*33a6c324SThomas Petazzoni reg = <0x3f0100 0x10>; 22*33a6c324SThomas Petazzoni #interrupt-cells = <1>; 23*33a6c324SThomas Petazzoni interrupt-controller; 24*33a6c324SThomas Petazzoni interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 25*33a6c324SThomas Petazzoni }; 26