1*4a073175SStefan AgnerFreescale Vybrid Miscellaneous System Control - Interrupt Router 2*4a073175SStefan Agner 3*4a073175SStefan AgnerThe MSCM IP contains multiple sub modules, this binding describes the second 4*4a073175SStefan Agnerblock of registers which control the interrupt router. The interrupt router 5*4a073175SStefan Agnerallows to configure the recipient of each peripheral interrupt. Furthermore 6*4a073175SStefan Agnerit controls the directed processor interrupts. The module is available in all 7*4a073175SStefan AgnerVybrid SoC's but is only really useful in dual core configurations (VF6xx 8*4a073175SStefan Agnerwhich comes with a Cortex-A5/Cortex-M4 combination). 9*4a073175SStefan Agner 10*4a073175SStefan AgnerRequired properties: 11*4a073175SStefan Agner- compatible: "fsl,vf610-mscm-ir" 12*4a073175SStefan Agner- reg: the register range of the MSCM Interrupt Router 13*4a073175SStefan Agner- fsl,cpucfg: The handle to the MSCM CPU configuration node, required 14*4a073175SStefan Agner to get the current CPU ID 15*4a073175SStefan Agner- interrupt-controller: Identifies the node as an interrupt controller 16*4a073175SStefan Agner- #interrupt-cells: Two cells, interrupt number and cells. 17*4a073175SStefan Agner The hardware interrupt number according to interrupt 18*4a073175SStefan Agner assignment of the interrupt router is required. 19*4a073175SStefan Agner Flags get passed only when using GIC as parent. Flags 20*4a073175SStefan Agner encoding as documented by the GIC bindings. 21*4a073175SStefan Agner 22*4a073175SStefan AgnerExample: 23*4a073175SStefan Agner mscm_ir: interrupt-controller@40001800 { 24*4a073175SStefan Agner compatible = "fsl,vf610-mscm-ir"; 25*4a073175SStefan Agner reg = <0x40001800 0x400>; 26*4a073175SStefan Agner fsl,cpucfg = <&mscm_cpucfg>; 27*4a073175SStefan Agner interrupt-controller; 28*4a073175SStefan Agner #interrupt-cells = <2>; 29*4a073175SStefan Agner interrupt-parent = <&intc>; 30*4a073175SStefan Agner } 31