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Searched refs:FPSR (Results 1 – 25 of 29) sorted by relevance

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/openbmc/qemu/target/hppa/
H A Dcpu.h159 FIELD(FPSR, ENA_I, 0, 1)
160 FIELD(FPSR, ENA_U, 1, 1)
161 FIELD(FPSR, ENA_O, 2, 1)
162 FIELD(FPSR, ENA_Z, 3, 1)
163 FIELD(FPSR, ENA_V, 4, 1)
164 FIELD(FPSR, ENABLES, 0, 5)
165 FIELD(FPSR, D, 5, 1)
166 FIELD(FPSR, T, 6, 1)
167 FIELD(FPSR, RM, 9, 2)
168 FIELD(FPSR, CQ, 11, 11)
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H A Dfpu_helper.c33 switch (FIELD_EX32(shadow, FPSR, RM)) { in HELPER()
49 d = FIELD_EX32(shadow, FPSR, D); in HELPER()
393 shadow = FIELD_DP32(shadow, FPSR, CQ0, FIELD_EX32(shadow, FPSR, C)); in update_fr0_cmp()
395 shadow = FIELD_DP32(shadow, FPSR, C, c); in update_fr0_cmp()
H A Dhelper.c204 fpsr, flg, ena, rm[FIELD_EX32(fpsr, FPSR, RM)]); in hppa_cpu_dump_state()
/openbmc/linux/arch/m68k/fpsp040/
H A Dkernel_ex.S51 | set FPSR exception status dz bit, condition code
57 | set exception status bit & accrued bits in FPSR
67 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR
68 fmovel #0,%FPSR |clr status bits (Z set)
73 fmovel #0,%FPSR |clr status bits (Z set)
84 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR
97 bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR
106 | set FPSR exception status operr bit, condition code
111 | set FPSR exception status operr bit, accrued operr bit
328 | and set the FPSR bits accordingly. See the MC68040 User's Manual
H A Dfpsp.h94 .set USER_FPSR,LV+68 | saved user FPSR
95 .set FPSR_CC,USER_FPSR+0 | FPSR condition code
96 .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient
97 .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception
98 .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception
220 | FPSR/FPCR bits
244 | FPSR individual bit masks
266 | FPSR combinations used in the FPSP
H A Dx_unimp.S55 | The following lines are used to ensure that the FPSR
61 fmovel #0,%FPSR |clear all user bits
H A Dgen_except.S86 | Or in the FPSR from the emulation with the USER_FPSR on the stack.
88 fmovel %FPSR,%d0
117 | Or in the FPSR from the emulation with the USER_FPSR on the stack.
119 fmovel %FPSR,%d0
133 | Or in the FPSR from the emulation with the USER_FPSR on the stack.
135 fmovel %FPSR,%d0
H A Dskeleton.S270 | This sample handler simply clears the nan bit in the FPSR.
281 fmovel %FPSR,-(%sp)
283 fmovel (%sp)+,%FPSR
H A Ddo_func.S170 fmovel #0,%FPSR |clr N flag
480 fmovemx PONE,%fp1-%fp1 |do not allow FPSR to be affected
502 | stacked FPSR to be correctly reported.
H A Dget_op.S539 fmovel #0,%FPSR |clr fpsr from decbin
544 | packed cases, but we must set the FPSR condition codes properly.
H A Ddecbin.S497 fmovel %FPSR,%d0 |get status register
499 fmovel %d0,%FPSR |return status reg w/o inex2
H A Dscale.S89 fmovel #0,%FPSR |clr status from above
H A Dx_operr.S230 fmovel #0,%FPSR
/openbmc/qemu/linux-user/arm/nwfpe/
H A Dfpsr.h40 typedef unsigned int FPSR; /* type for floating point status register */ typedef
H A Dfpa11.h73 /* 96 */ FPSR fpsr; /* floating point status register */
H A Dfpa11.inl30 static inline void writeFPSR(FPSR reg)
/openbmc/linux/arch/arm/nwfpe/
H A Dfpsr.h29 typedef unsigned int FPSR; /* type for floating point status register */ typedef
H A Dfpa11.h69 /* 96 */ FPSR fpsr; /* floating point status register */
H A Dfpa11.inl31 static inline void writeFPSR(FPSR reg)
/openbmc/linux/arch/m68k/ifpsp060/src/
H A Dfpsp.S9449 # answer is inexact, so set INEX2 and AINEX in the user's FPSR.
10126 # - Set FPSR exception status dz bit, ccode inf bit, and #
10149 # - set FPSR exception status operr bit, condition code #
11626 fmov.l &0x0,%fpsr # clear FPSR
11666 fmov.l &0x0,%fpsr # clear FPSR
12276 # now, round to extended(and don't alter the FPSR).
12297 fmov.l &0x0,%fpsr # clear FPSR
13056 # now, round to extended(and don't alter the FPSR).
13077 fmov.l &0x0,%fpsr # clear FPSR
13326 # then store the resulting FPSR bits. #
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/openbmc/linux/Documentation/arch/arm64/
H A Dsve.rst141 * This record is supplementary to fpsimd_context. The FPSR and FPCR registers
514 * FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
532 +---- //// --+ FPSR | |
571 * 2 32-bit status/control registers FPSR, FPCR
590 FPSR | |
/openbmc/linux/arch/m68k/ifpsp060/
H A Dfskeleton.S189 | bit in the FPSR, and does an "rte". The instruction that caused the
190 | bsun will now be re-executed but with the NaN FPSR bit cleared.
H A DCHANGES38 Inexact FPSR bit. Emulation now does not set Inexact for
H A Dfplsp.doc91 Upon return, fp0 holds the correct result. The FPSR is
/openbmc/linux/drivers/net/wireless/admtek/
H A Dadm8211.h82 __le32 FPSR; /* 0x108 */ member

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