13ebdd119Saurel32 /* 23ebdd119Saurel32 NetWinder Floating Point Emulator 33ebdd119Saurel32 (c) Rebel.com, 1998-1999 43ebdd119Saurel32 53ebdd119Saurel32 Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 63ebdd119Saurel32 73ebdd119Saurel32 This program is free software; you can redistribute it and/or modify 83ebdd119Saurel32 it under the terms of the GNU General Public License as published by 93ebdd119Saurel32 the Free Software Foundation; either version 2 of the License, or 103ebdd119Saurel32 (at your option) any later version. 113ebdd119Saurel32 123ebdd119Saurel32 This program is distributed in the hope that it will be useful, 133ebdd119Saurel32 but WITHOUT ANY WARRANTY; without even the implied warranty of 143ebdd119Saurel32 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 153ebdd119Saurel32 GNU General Public License for more details. 163ebdd119Saurel32 173ebdd119Saurel32 You should have received a copy of the GNU General Public License 1870539e18SBlue Swirl along with this program; if not, see <http://www.gnu.org/licenses/>. 193ebdd119Saurel32 */ 203ebdd119Saurel32 21*2a6a4076SMarkus Armbruster #ifndef FPSR_H 22*2a6a4076SMarkus Armbruster #define FPSR_H 233ebdd119Saurel32 243ebdd119Saurel32 /* 253ebdd119Saurel32 The FPSR is a 32 bit register consisting of 4 parts, each exactly 263ebdd119Saurel32 one byte. 273ebdd119Saurel32 283ebdd119Saurel32 SYSTEM ID 293ebdd119Saurel32 EXCEPTION TRAP ENABLE BYTE 303ebdd119Saurel32 SYSTEM CONTROL BYTE 313ebdd119Saurel32 CUMULATIVE EXCEPTION FLAGS BYTE 323ebdd119Saurel32 333ebdd119Saurel32 The FPCR is a 32 bit register consisting of bit flags. 343ebdd119Saurel32 */ 353ebdd119Saurel32 363ebdd119Saurel32 /* SYSTEM ID 373ebdd119Saurel32 ------------ 383ebdd119Saurel32 Note: the system id byte is read only */ 393ebdd119Saurel32 403ebdd119Saurel32 typedef unsigned int FPSR; /* type for floating point status register */ 413ebdd119Saurel32 typedef unsigned int FPCR; /* type for floating point control register */ 423ebdd119Saurel32 433ebdd119Saurel32 #define MASK_SYSID 0xff000000 443ebdd119Saurel32 #define BIT_HARDWARE 0x80000000 453ebdd119Saurel32 #define FP_EMULATOR 0x01000000 /* System ID for emulator */ 463ebdd119Saurel32 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ 473ebdd119Saurel32 483ebdd119Saurel32 /* EXCEPTION TRAP ENABLE BYTE 493ebdd119Saurel32 ----------------------------- */ 503ebdd119Saurel32 513ebdd119Saurel32 #define MASK_TRAP_ENABLE 0x00ff0000 523ebdd119Saurel32 #define MASK_TRAP_ENABLE_STRICT 0x001f0000 533ebdd119Saurel32 #define BIT_IXE 0x00100000 /* inexact exception enable */ 543ebdd119Saurel32 #define BIT_UFE 0x00080000 /* underflow exception enable */ 553ebdd119Saurel32 #define BIT_OFE 0x00040000 /* overflow exception enable */ 563ebdd119Saurel32 #define BIT_DZE 0x00020000 /* divide by zero exception enable */ 573ebdd119Saurel32 #define BIT_IOE 0x00010000 /* invalid operation exception enable */ 583ebdd119Saurel32 593ebdd119Saurel32 /* SYSTEM CONTROL BYTE 603ebdd119Saurel32 ---------------------- */ 613ebdd119Saurel32 623ebdd119Saurel32 #define MASK_SYSTEM_CONTROL 0x0000ff00 633ebdd119Saurel32 #define MASK_TRAP_STRICT 0x00001f00 643ebdd119Saurel32 653ebdd119Saurel32 #define BIT_AC 0x00001000 /* use alternative C-flag definition 663ebdd119Saurel32 for compares */ 673ebdd119Saurel32 #define BIT_EP 0x00000800 /* use expanded packed decimal format */ 683ebdd119Saurel32 #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ 693ebdd119Saurel32 #define BIT_NE 0x00000200 /* NaN exception bit */ 703ebdd119Saurel32 #define BIT_ND 0x00000100 /* no denormalized numbers bit */ 713ebdd119Saurel32 723ebdd119Saurel32 /* CUMULATIVE EXCEPTION FLAGS BYTE 733ebdd119Saurel32 ---------------------------------- */ 743ebdd119Saurel32 753ebdd119Saurel32 #define MASK_EXCEPTION_FLAGS 0x000000ff 763ebdd119Saurel32 #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f 773ebdd119Saurel32 783ebdd119Saurel32 #define BIT_IXC 0x00000010 /* inexact exception flag */ 793ebdd119Saurel32 #define BIT_UFC 0x00000008 /* underflow exception flag */ 803ebdd119Saurel32 #define BIT_OFC 0x00000004 /* overfloat exception flag */ 813ebdd119Saurel32 #define BIT_DZC 0x00000002 /* divide by zero exception flag */ 823ebdd119Saurel32 #define BIT_IOC 0x00000001 /* invalid operation exception flag */ 833ebdd119Saurel32 843ebdd119Saurel32 /* Floating Point Control Register 853ebdd119Saurel32 ----------------------------------*/ 863ebdd119Saurel32 873ebdd119Saurel32 #define BIT_RU 0x80000000 /* rounded up bit */ 883ebdd119Saurel32 #define BIT_IE 0x10000000 /* inexact bit */ 893ebdd119Saurel32 #define BIT_MO 0x08000000 /* mantissa overflow bit */ 903ebdd119Saurel32 #define BIT_EO 0x04000000 /* exponent overflow bit */ 913ebdd119Saurel32 #define BIT_SB 0x00000800 /* store bounce */ 923ebdd119Saurel32 #define BIT_AB 0x00000400 /* arithmetic bounce */ 933ebdd119Saurel32 #define BIT_RE 0x00000200 /* rounding exception */ 943ebdd119Saurel32 #define BIT_DA 0x00000100 /* disable FPA */ 953ebdd119Saurel32 963ebdd119Saurel32 #define MASK_OP 0x00f08010 /* AU operation code */ 973ebdd119Saurel32 #define MASK_PR 0x00080080 /* AU precision */ 983ebdd119Saurel32 #define MASK_S1 0x00070000 /* AU source register 1 */ 993ebdd119Saurel32 #define MASK_S2 0x00000007 /* AU source register 2 */ 1003ebdd119Saurel32 #define MASK_DS 0x00007000 /* AU destination register */ 1013ebdd119Saurel32 #define MASK_RM 0x00000060 /* AU rounding mode */ 1023ebdd119Saurel32 #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ 1033ebdd119Saurel32 #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ 1043ebdd119Saurel32 #define MASK_WFC MASK_RESET 1053ebdd119Saurel32 #define MASK_RFC ~MASK_RESET 1063ebdd119Saurel32 1073ebdd119Saurel32 #endif 108