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Searched refs:CP0_Config5 (Results 1 – 16 of 16) sorted by relevance

/openbmc/qemu/linux-user/mips/
H A Dtarget_prctl.h16 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { in do_prctl_get_fp_mode()
26 bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE); in do_prctl_set_fp_mode()
75 env->CP0_Config5 |= (1 << CP0C5_FRE); in do_prctl_set_fp_mode()
80 env->CP0_Config5 &= ~(1 << CP0C5_FRE); in do_prctl_set_fp_mode()
H A Dcpu_loop.c284 env->CP0_Config5 |= (1 << CP0C5_FRE); in target_cpu_copy_regs()
/openbmc/qemu/target/mips/
H A Dinternal.h41 int32_t CP0_Config5; member
351 (env->CP0_Config5 & (1 << CP0C5_SBRI))) { in compute_hflags()
402 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { in compute_hflags()
407 if (env->CP0_Config5 & (1 << CP0C5_FRE)) { in compute_hflags()
H A Dmsa.c34 env->CP0_Config5 |= 1 << CP0C5_MSAEn; in msa_reset()
H A Dcpu.c111 env->CP0_Config4, env->CP0_Config5); in mips_cpu_dump_state()
170 if (env->CP0_Config5 & (1 << CP0C5_VP)) { in mips_cpu_has_work()
210 env->CP0_Config5 = env->cpu_model->CP0_Config5; in mips_cpu_reset_hold()
302 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in mips_cpu_reset_hold()
H A Dcpu-defs.c.inc384 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
409 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
444 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
487 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
528 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
759 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
799 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
911 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
H A Dkvm.c904 &env->CP0_Config5, in kvm_mips_put_cp0_registers()
1113 err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG5, &env->CP0_Config5); in kvm_mips_get_cp0_registers()
H A Dcpu.h926 int32_t CP0_Config5; member
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dtlb_helper.c85 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbinv()
115 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbwi()
171 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbp()
234 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_helper_tlbr()
396 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_map_address()
1315 env->CP0_Config5 & (1 << CP0C5_CV))) { in mips_cpu_do_interrupt()
1366 bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); in r4k_invalidate_tlb()
H A Dcp0_helper.c1277 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1279 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? in helper_mtc0_config5()
1337 if ((env->CP0_Config5 >> CP0C5_MI) & 1) { in helper_mtc0_watchhi()
/openbmc/qemu/target/mips/tcg/
H A Dfpu_helper.c51 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_cfc1()
62 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_cfc1()
63 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1; in helper_cfc1()
96 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_ctc1()
108 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_ctc1()
120 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_ctc1()
121 env->CP0_Config5 &= ~(1 << CP0C5_FRE); in helper_ctc1()
132 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_ctc1()
133 env->CP0_Config5 |= (1 << CP0C5_FRE); in helper_ctc1()
H A Dop_helper.c230 return (env->CP0_Config5 >> CP0C5_XNP) & 1; in helper_rdhwr_xnp()
H A Dtranslate.h29 int32_t CP0_Config5; member
H A Dtranslate.c1649 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { in check_xnp()
1703 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { in check_nms()
1715 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && in check_nms_dl_il_sl_tl_l2c()
1720 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { in check_nms_dl_il_sl_tl_l2c()
1731 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { in check_eva()
5556 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); in gen_mfc0()
7032 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); in gen_dmfc0()
15073 ctx->CP0_Config5 = env->CP0_Config5; in mips_tr_init_disas_context()
15081 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; in mips_tr_init_disas_context()
15082 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; in mips_tr_init_disas_context()
[all …]
/openbmc/qemu/hw/mips/
H A Dcps.c60 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env); in cpu_mips_itu_supported()
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c305 VMSTATE_INT32(env.CP0_Config5, MIPSCPU),