Home
last modified time | relevance | path

Searched refs:CONFIG_SYS_PCIE1_MEM_PHYS (Results 1 – 25 of 72) sorted by relevance

123

/openbmc/u-boot/board/varisys/cyrus/
H A Dtlb.c59 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
65 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
70 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/openbmc/u-boot/board/freescale/t4rdb/
H A Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
61 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
66 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/openbmc/u-boot/board/freescale/common/p_corenet/
H A Dtlb.c94 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
100 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
105 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/openbmc/u-boot/board/freescale/t4qds/
H A Dtlb.c68 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
74 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
79 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
/openbmc/u-boot/include/configs/
H A Dxpedite517x.h279 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
343 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
347 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
351 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
H A Dcontrolcenterd.h212 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
215 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
H A Dsbc8641d.h261 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS macro
346 #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
349 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
H A DMPC8548CDS.h351 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull macro
354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 macro
H A Dcyrus.h243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
H A DP1022DS.h400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
H A DMPC8536DS.h400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull macro
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 macro
H A DMPC8572DS.h419 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull macro
422 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 macro
H A DP2041RDB.h359 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
362 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
H A Dcorenet_ds.h367 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull macro
370 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 macro
/openbmc/u-boot/board/gdsys/p1022/
H A Dtlb.c52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
56 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dtlb.c60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
69 (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
/openbmc/u-boot/board/xes/xpedite550x/
H A Dtlb.c54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/xes/xpedite537x/
H A Dtlb.c54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/freescale/b4860qds/
H A Dtlb.c66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
71 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
/openbmc/u-boot/board/mpc8308_p1m/
H A Dmpc8308_p1m.c28 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/freescale/p1_twr/
H A Dtlb.c54 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/Arcturus/ucp1020/
H A Dtlb.c52 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/freescale/p1010rdb/
H A Dtlb.c55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/freescale/c29xpcie/
H A Dtlb.c38 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dtlb.c60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,

123