1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 287e29878SAndy Fleming /* 387e29878SAndy Fleming * Author: Adrian Cox 487e29878SAndy Fleming * Based on corenet_ds tlb code 587e29878SAndy Fleming */ 687e29878SAndy Fleming 787e29878SAndy Fleming #include <common.h> 887e29878SAndy Fleming #include <asm/mmu.h> 987e29878SAndy Fleming 1087e29878SAndy Fleming struct fsl_e_tlb_entry tlb_table[] = { 1187e29878SAndy Fleming /* TLB 0 - for temp stack in cache */ 1287e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 1387e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS, 1487e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 1587e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 1687e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 1787e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 1887e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 1987e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 2087e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 2187e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 2287e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 2387e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 2487e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 2587e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 2687e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 2787e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 2887e29878SAndy Fleming 2987e29878SAndy Fleming /* TLB 1 */ 3087e29878SAndy Fleming /* *I*** - Covers boot page */ 3187e29878SAndy Fleming #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 3287e29878SAndy Fleming /* 3387e29878SAndy Fleming * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 3487e29878SAndy Fleming * SRAM is at 0xfff00000, it covered the 0xfffff000. 3587e29878SAndy Fleming */ 3687e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 3787e29878SAndy Fleming MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 3887e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_1M, 1), 3987e29878SAndy Fleming #else 4087e29878SAndy Fleming SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 4187e29878SAndy Fleming MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 4287e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 1), 4387e29878SAndy Fleming #endif 4487e29878SAndy Fleming 4587e29878SAndy Fleming /* *I*G* - CCSRBAR */ 4687e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 4787e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 4887e29878SAndy Fleming 0, 1, BOOKE_PAGESZ_16M, 1), 4987e29878SAndy Fleming 5087e29878SAndy Fleming /* Local Bus */ 5187e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS, 5287e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 5387e29878SAndy Fleming 0, 2, BOOKE_PAGESZ_64K, 1), 5487e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS, 5587e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 5687e29878SAndy Fleming 0, 3, BOOKE_PAGESZ_4K, 1), 5787e29878SAndy Fleming 5887e29878SAndy Fleming /* *I*G* - PCI */ 5987e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 6087e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6187e29878SAndy Fleming 0, 4, BOOKE_PAGESZ_1G, 1), 6287e29878SAndy Fleming 6387e29878SAndy Fleming /* *I*G* - PCI */ 6487e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 6587e29878SAndy Fleming CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 6687e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 6787e29878SAndy Fleming 0, 5, BOOKE_PAGESZ_256M, 1), 6887e29878SAndy Fleming 6987e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 7087e29878SAndy Fleming CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 7187e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 7287e29878SAndy Fleming 0, 6, BOOKE_PAGESZ_256M, 1), 7387e29878SAndy Fleming 7487e29878SAndy Fleming /* *I*G* - PCI I/O */ 7587e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 7687e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 7787e29878SAndy Fleming 0, 7, BOOKE_PAGESZ_256K, 1), 7887e29878SAndy Fleming 7987e29878SAndy Fleming /* Bman/Qman */ 8087e29878SAndy Fleming #ifdef CONFIG_SYS_BMAN_MEM_PHYS 8187e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 8287e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 8387e29878SAndy Fleming 0, 9, BOOKE_PAGESZ_1M, 1), 8487e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 8587e29878SAndy Fleming CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 8687e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 8787e29878SAndy Fleming 0, 10, BOOKE_PAGESZ_1M, 1), 8887e29878SAndy Fleming #endif 8987e29878SAndy Fleming #ifdef CONFIG_SYS_QMAN_MEM_PHYS 9087e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 9187e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 9287e29878SAndy Fleming 0, 11, BOOKE_PAGESZ_1M, 1), 9387e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 9487e29878SAndy Fleming CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 9587e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 9687e29878SAndy Fleming 0, 12, BOOKE_PAGESZ_1M, 1), 9787e29878SAndy Fleming #endif 9887e29878SAndy Fleming #ifdef CONFIG_SYS_DCSRBAR_PHYS 9987e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 10087e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 10187e29878SAndy Fleming 0, 13, BOOKE_PAGESZ_4M, 1), 10287e29878SAndy Fleming #endif 10387e29878SAndy Fleming }; 10487e29878SAndy Fleming 10587e29878SAndy Fleming int num_tlb_entries = ARRAY_SIZE(tlb_table); 106