/openbmc/qemu/target/rx/ |
H A D | insns.decode | 24 &rr rd rs 25 &ri rd imm 26 &rrr rd rs rs2 27 &rri rd imm rs2 28 &rm rd rs ld mi 31 &mcnd ld sz rd cd 43 @b2_rds .... .... .... rd:4 &rr rs=%b2_r_0 44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8 45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0 46 @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0 [all …]
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H A D | disas.c | 173 int ld, int mi, int rs, int rd) in prt_ldmi() argument 180 prt("%s\t%s[r%d]%s, r%d", insn, dsp, rs, sizes[mi], rd); in prt_ldmi() 182 prt("%s\tr%d, r%d", insn, rs, rd); in prt_ldmi() 186 static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd) in prt_ir() argument 189 prt("%s\t#%d, r%d", insn, imm, rd); in prt_ir() 191 prt("%s\t#0x%08x, r%d", insn, imm, rd); in prt_ir() 200 size[a->sz], a->rs, a->dsp << a->sz, a->rd); in trans_MOV_rm() 203 size[a->sz], a->rs, a->rd); in trans_MOV_rm() 213 size[a->sz], a->dsp << a->sz, a->rs, a->rd); in trans_MOV_mr() 216 size[a->sz], a->rs, a->rd); in trans_MOV_mr() [all …]
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/openbmc/linux/arch/arm/net/ |
H A D | bpf_jit_32.h | 162 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument 164 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument 168 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument 169 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument 170 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument 171 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument 172 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument 173 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument 175 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument 176 #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm) argument [all …]
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/openbmc/linux/arch/arm/include/debug/ |
H A D | samsung.S | 12 .macro fifo_level_s5pv210 rd, rx 13 ldr \rd, [\rx, # S3C2410_UFSTAT] 14 ARM_BE8(rev \rd, \rd) 15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK 18 .macro fifo_full_s5pv210 rd, rx 19 ldr \rd, [\rx, # S3C2410_UFSTAT] 20 ARM_BE8(rev \rd, \rd) 21 tst \rd, #S5PV210_UFSTAT_TXFULL 27 .macro fifo_level_s3c2440 rd, rx 28 ldr \rd, [\rx, # S3C2410_UFSTAT] [all …]
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H A D | 8250.S | 15 .macro store, rd, rx:vararg 16 ARM_BE8(rev \rd, \rd) 17 str \rd, \rx 18 ARM_BE8(rev \rd, \rd) 21 .macro load, rd, rx:vararg 22 ldr \rd, \rx 23 ARM_BE8(rev \rd, \rd) 26 .macro store, rd, rx:vararg 27 strb \rd, \rx 30 .macro load, rd, rx:vararg [all …]
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H A D | msm.S | 14 .macro senduart, rd, rx 15 ARM_BE8(rev \rd, \rd ) 17 str \rd, [\rx, #0x70] 20 .macro waituartcts,rd,rx 23 .macro waituarttxrdy, rd, rx 25 ldr \rd, [\rx, #0x08] 26 ARM_BE8(rev \rd, \rd ) 27 tst \rd, #0x08 30 1001: ldr \rd, [\rx, #0x14] 31 ARM_BE8(rev \rd, \rd ) [all …]
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H A D | icedcc.S | 15 .macro senduart, rd, rx 16 mcr p14, 0, \rd, c0, c5, 0 19 .macro busyuart, rd, rx 26 .macro waituartcts, rd, rx 29 .macro waituarttxrdy, rd, rx 30 mov \rd, #0x2000000 32 subs \rd, \rd, #1 42 .macro senduart, rd, rx 43 mcr p14, 0, \rd, c8, c0, 0 46 .macro busyuart, rd, rx [all …]
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/openbmc/linux/arch/riscv/net/ |
H A D | bpf_jit.h | 229 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument 233 (rd << 7) | opcode; in rv_r_insn() 236 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument 238 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn() 259 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) in rv_u_insn() argument 261 return (imm31_12 << 12) | (rd << 7) | opcode; in rv_u_insn() 264 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode) in rv_j_insn() argument 271 return (imm << 12) | (rd << 7) | opcode; in rv_j_insn() 275 u8 funct3, u8 rd, u8 opcode) in rv_amo_insn() argument 279 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn() [all …]
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H A D | bpf_jit_comp32.c | 111 static void emit_imm(const s8 rd, s32 imm, struct rv_jit_context *ctx) in emit_imm() argument 117 emit(rv_lui(rd, upper), ctx); in emit_imm() 118 emit(rv_addi(rd, rd, lower), ctx); in emit_imm() 120 emit(rv_addi(rd, RV_REG_ZERO, lower), ctx); in emit_imm() 124 static void emit_imm32(const s8 *rd, s32 imm, struct rv_jit_context *ctx) in emit_imm32() argument 127 emit_imm(lo(rd), imm, ctx); in emit_imm32() 131 emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); in emit_imm32() 133 emit(rv_addi(hi(rd), RV_REG_ZERO, -1), ctx); in emit_imm32() 136 static void emit_imm64(const s8 *rd, s32 imm_hi, s32 imm_lo, in emit_imm64() argument 139 emit_imm(lo(rd), imm_lo, ctx); in emit_imm64() [all …]
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H A D | bpf_jit_comp64.c | 145 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) in emit_addr() argument 161 emit(rv_auipc(rd, upper), ctx); in emit_addr() 162 emit(rv_addi(rd, rd, lower), ctx); in emit_addr() 167 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) in emit_imm() argument 188 emit_lui(rd, upper, ctx); in emit_imm() 191 emit_li(rd, lower, ctx); in emit_imm() 195 emit_addiw(rd, rd, lower, ctx); in emit_imm() 203 emit_imm(rd, upper, ctx); in emit_imm() 205 emit_slli(rd, rd, shift, ctx); in emit_imm() 207 emit_addi(rd, rd, lower, ctx); in emit_imm() [all …]
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/openbmc/u-boot/post/lib_powerpc/ |
H A D | cpu_asm.h | 113 #define ASM_1(opcode, rd) ((opcode) + \ argument 114 ((rd) << 21)) 117 #define ASM_11(opcode, rd, rs) ((opcode) + \ argument 118 ((rd) << 21) + \ 123 #define ASM_11X(opcode, rd, rs) ((opcode) + \ argument 125 ((rd) << 16)) 126 #define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ argument 127 ((rd) << 21) + \ 130 #define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ argument 131 ((rd) << 21) + \ [all …]
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/openbmc/linux/drivers/gpu/drm/msm/ |
H A D | msm_rd.c | 97 static void rd_write(struct msm_rd_state *rd, const void *buf, int sz) in rd_write() argument 99 struct circ_buf *fifo = &rd->fifo; in rd_write() 106 wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open); in rd_write() 107 if (!rd->open) in rd_write() 114 n = min(sz, circ_space_to_end(&rd->fifo)); in rd_write() 121 wake_up_all(&rd->fifo_event); in rd_write() 125 static void rd_write_section(struct msm_rd_state *rd, in rd_write_section() argument 128 rd_write(rd, &type, 4); in rd_write_section() 129 rd_write(rd, &sz, 4); in rd_write_section() 130 rd_write(rd, buf, sz); in rd_write_section() [all …]
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/openbmc/qemu/target/avr/ |
H A D | disas.c | 133 INSN(ADD, "r%d, r%d", a->rd, a->rr) 134 INSN(ADC, "r%d, r%d", a->rd, a->rr) 135 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm) 136 INSN(SUB, "r%d, r%d", a->rd, a->rr) 137 INSN(SUBI, "r%d, %d", a->rd, a->imm) 138 INSN(SBC, "r%d, r%d", a->rd, a->rr) 139 INSN(SBCI, "r%d, %d", a->rd, a->imm) 140 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm) 141 INSN(AND, "r%d, r%d", a->rd, a->rr) 142 INSN(ANDI, "r%d, %d", a->rd, a->imm) [all …]
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H A D | insn.decode | 26 %rd 4:5 42 &rd_rr rd rr 43 &rd_imm rd imm 45 @op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr 46 @op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6 47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8 48 @fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b 66 COM 1001 010 rd:5 0000 67 NEG 1001 010 rd:5 0001 68 INC 1001 010 rd:5 0011 [all …]
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/openbmc/linux/drivers/powercap/ |
H A D | intel_rapl_common.c | 123 static bool is_pl_valid(struct rapl_domain *rd, int pl) in is_pl_valid() argument 127 return rd->rpl[pl].name ? true : false; in is_pl_valid() 130 static int get_pl_lock_prim(struct rapl_domain *rd, int pl) in get_pl_lock_prim() argument 132 if (rd->rp->priv->type == RAPL_IF_TPMI) { in get_pl_lock_prim() 149 if (rd->rp->priv->limits[rd->id] & BIT(POWER_LIMIT2)) in get_pl_lock_prim() 154 static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim) in get_pl_prim() argument 160 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) in get_pl_prim() 169 return get_pl_lock_prim(rd, pl); in get_pl_prim() 174 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) in get_pl_prim() 183 return get_pl_lock_prim(rd, pl); in get_pl_prim() [all …]
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/openbmc/linux/kernel/time/ |
H A D | sched_clock.c | 85 struct clock_read_data *rd; in sched_clock_noinstr() local 91 rd = cd.read_data + (seq & 1); in sched_clock_noinstr() 93 cyc = (rd->read_sched_clock() - rd->epoch_cyc) & in sched_clock_noinstr() 94 rd->sched_clock_mask; in sched_clock_noinstr() 95 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock_noinstr() 120 static void update_clock_read_data(struct clock_read_data *rd) in update_clock_read_data() argument 123 cd.read_data[1] = *rd; in update_clock_read_data() 129 cd.read_data[0] = *rd; in update_clock_read_data() 142 struct clock_read_data rd; in update_sched_clock() local 144 rd = cd.read_data[0]; in update_sched_clock() [all …]
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/openbmc/linux/fs/jffs2/ |
H A D | write.c | 206 struct jffs2_raw_dirent *rd, const unsigned char *name, in jffs2_write_dirent() argument 218 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent() 219 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent() 221 D1(if(je32_to_cpu(rd->hdr_crc) != crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)) { in jffs2_write_dirent() 231 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent() 232 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent() 237 vecs[0].iov_base = rd; in jffs2_write_dirent() 238 vecs[0].iov_len = sizeof(*rd); in jffs2_write_dirent() 246 fd->version = je32_to_cpu(rd->version); in jffs2_write_dirent() 247 fd->ino = je32_to_cpu(rd->ino); in jffs2_write_dirent() [all …]
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/openbmc/linux/arch/parisc/net/ |
H A D | bpf_jit_comp64.c | 70 static void emit_hppa_copy(const s8 rs, const s8 rd, struct hppa_jit_context *ctx) in emit_hppa_copy() argument 72 REG_SET_SEEN(ctx, rd); in emit_hppa_copy() 73 if (OPTIMIZE_HPPA && (rs == rd)) in emit_hppa_copy() 76 emit(hppa_copy(rs, rd), ctx); in emit_hppa_copy() 135 static void emit_imm32(u8 rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm32() argument 139 REG_SET_SEEN(ctx, rd); in emit_imm32() 141 emit(hppa_ldi(imm, rd), ctx); in emit_imm32() 145 emit(hppa_ldo(lower, HPPA_REG_ZERO, rd), ctx); in emit_imm32() 148 emit(hppa_ldil(imm, rd), ctx); in emit_imm32() 151 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm32() [all …]
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H A D | bpf_jit_comp32.c | 120 static void emit_hppa_copy(const s8 rs, const s8 rd, struct hppa_jit_context *ctx) in emit_hppa_copy() argument 122 REG_SET_SEEN(ctx, rd); in emit_hppa_copy() 123 if (OPTIMIZE_HPPA && (rs == rd)) in emit_hppa_copy() 126 emit(hppa_copy(rs, rd), ctx); in emit_hppa_copy() 141 static void emit_imm(const s8 rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm() argument 145 REG_SET_SEEN(ctx, rd); in emit_imm() 147 emit(hppa_ldi(imm, rd), ctx); in emit_imm() 150 emit(hppa_ldil(imm, rd), ctx); in emit_imm() 153 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm() 156 static void emit_imm32(const s8 *rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm32() argument [all …]
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/openbmc/qemu/target/sparc/ |
H A D | insns.decode | 21 SETHI 00 rd:5 100 i:22 38 &r_r_ri rd rs1 rs2_or_imm imm:bool 39 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 40 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri 42 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool 43 @r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc 44 @r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0 45 @r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1 47 &r_r_r rd rs1 rs2 48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r [all …]
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/openbmc/qemu/target/mips/tcg/ |
H A D | loong_translate.c | 28 static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt, in gen_lext_DIV_G() argument 34 if (rd == 0) { in gen_lext_DIV_G() 53 tcg_gen_movi_tl(cpu_gpr[rd], 0); in gen_lext_DIV_G() 59 tcg_gen_mov_tl(cpu_gpr[rd], t0); in gen_lext_DIV_G() 63 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); in gen_lext_DIV_G() 65 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); in gen_lext_DIV_G() 74 return gen_lext_DIV_G(s, a->rd, a->rs, a->rt, false); in trans_DIV_G() 79 return gen_lext_DIV_G(s, a->rd, a->rs, a->rt, true); in trans_DDIV_G() 82 static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt, in gen_lext_DIVU_G() argument 88 if (rd == 0) { in gen_lext_DIVU_G() [all …]
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H A D | tx79_translate.c | 67 gen_store_gpr(cpu_HI[1], a->rd); in trans_MFHI1() 74 gen_store_gpr(cpu_LO[1], a->rd); in trans_MFLO1() 122 if (a->rd == 0) { in trans_parallel_arith() 133 gen_logic_i64(cpu_gpr[a->rd], ax, bx); in trans_parallel_arith() 138 gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); in trans_parallel_arith() 239 if (a->rd == 0) { in trans_parallel_compare() 259 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); in trans_parallel_compare() 268 tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); in trans_parallel_compare() 421 if (a->rd == 0) { in trans_PPACW() 434 tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); in trans_PPACW() [all …]
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/openbmc/linux/arch/loongarch/net/ |
H A D | bpf_jit.h | 85 static inline void move_addr(struct jit_ctx *ctx, enum loongarch_gpr rd, u64 addr) in move_addr() argument 91 emit_insn(ctx, lu12iw, rd, imm_31_12); in move_addr() 95 emit_insn(ctx, ori, rd, rd, imm_11_0); in move_addr() 99 emit_insn(ctx, lu32id, rd, imm_51_32); in move_addr() 103 emit_insn(ctx, lu52id, rd, rd, imm_63_52); in move_addr() 106 static inline void move_imm(struct jit_ctx *ctx, enum loongarch_gpr rd, long imm, bool is32) in move_imm() argument 112 emit_insn(ctx, or, rd, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_ZERO); in move_imm() 118 emit_insn(ctx, addiw, rd, LOONGARCH_GPR_ZERO, imm); in move_imm() 124 emit_insn(ctx, ori, rd, LOONGARCH_GPR_ZERO, imm); in move_imm() 132 emit_insn(ctx, lu52id, rd, LOONGARCH_GPR_ZERO, imm_63_52); in move_imm() [all …]
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/openbmc/u-boot/arch/arm/include/debug/ |
H A D | 8250.S | 15 .macro store, rd, rx:vararg 16 str \rd, \rx 19 .macro load, rd, rx:vararg 20 ldr \rd, \rx 23 .macro store, rd, rx:vararg 24 strb \rd, \rx 27 .macro load, rd, rx:vararg 28 ldrb \rd, \rx 34 .macro senduart,rd,rx 35 store \rd, [\rx, #UART_TX << UART_SHIFT] [all …]
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/openbmc/linux/arch/sparc/include/asm/ |
H A D | head_32.h | 13 rd %psr, %l0; b label; rd %wim, %l3; nop; 16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7; 17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7; 21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3; 38 rd %psr, %l0; 42 rd %psr,%l0; \ 50 rd %psr,%l0; \ 59 b getcc_trap_handler; rd %psr, %l0; nop; nop; 63 b setcc_trap_handler; rd %psr, %l0; nop; nop; 67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop; [all …]
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