1865f3bb9SMichael Rolnik# 2865f3bb9SMichael Rolnik# AVR instruction decode definitions. 3865f3bb9SMichael Rolnik# 4865f3bb9SMichael Rolnik# Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com> 5865f3bb9SMichael Rolnik# 6865f3bb9SMichael Rolnik# This library is free software; you can redistribute it and/or 7865f3bb9SMichael Rolnik# modify it under the terms of the GNU Lesser General Public 8865f3bb9SMichael Rolnik# License as published by the Free Software Foundation; either 9865f3bb9SMichael Rolnik# version 2.1 of the License, or (at your option) any later version. 10865f3bb9SMichael Rolnik# 11865f3bb9SMichael Rolnik# This library is distributed in the hope that it will be useful, 12865f3bb9SMichael Rolnik# but WITHOUT ANY WARRANTY; without even the implied warranty of 13865f3bb9SMichael Rolnik# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14865f3bb9SMichael Rolnik# Lesser General Public License for more details. 15865f3bb9SMichael Rolnik# 16865f3bb9SMichael Rolnik# You should have received a copy of the GNU Lesser General Public 17865f3bb9SMichael Rolnik# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18865f3bb9SMichael Rolnik# 19865f3bb9SMichael Rolnik 20865f3bb9SMichael Rolnik# 21865f3bb9SMichael Rolnik# regs_16_31_by_one = [16 .. 31] 22865f3bb9SMichael Rolnik# regs_16_23_by_one = [16 .. 23] 23865f3bb9SMichael Rolnik# regs_24_30_by_two = [24, 26, 28, 30] 24865f3bb9SMichael Rolnik# regs_00_30_by_two = [0, 2, 4, 6, 8, .. 30] 25865f3bb9SMichael Rolnik 26865f3bb9SMichael Rolnik%rd 4:5 27865f3bb9SMichael Rolnik%rr 9:1 0:4 28865f3bb9SMichael Rolnik 29865f3bb9SMichael Rolnik%rd_a 4:4 !function=to_regs_16_31_by_one 30865f3bb9SMichael Rolnik%rd_b 4:3 !function=to_regs_16_23_by_one 31865f3bb9SMichael Rolnik%rd_c 4:2 !function=to_regs_24_30_by_two 32865f3bb9SMichael Rolnik%rr_a 0:4 !function=to_regs_16_31_by_one 33865f3bb9SMichael Rolnik%rr_b 0:3 !function=to_regs_16_23_by_one 34865f3bb9SMichael Rolnik 35865f3bb9SMichael Rolnik%imm6 6:2 0:4 36865f3bb9SMichael Rolnik%imm8 8:4 0:4 37865f3bb9SMichael Rolnik 38865f3bb9SMichael Rolnik%io_imm 9:2 0:4 39865f3bb9SMichael Rolnik%ldst_d_imm 13:1 10:2 0:3 40865f3bb9SMichael Rolnik 41865f3bb9SMichael Rolnik 42865f3bb9SMichael Rolnik&rd_rr rd rr 43865f3bb9SMichael Rolnik&rd_imm rd imm 44865f3bb9SMichael Rolnik 45865f3bb9SMichael Rolnik@op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr 46865f3bb9SMichael Rolnik@op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6 47865f3bb9SMichael Rolnik@op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8 48865f3bb9SMichael Rolnik@fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b 49865f3bb9SMichael Rolnik 50865f3bb9SMichael Rolnik# 51865f3bb9SMichael Rolnik# Arithmetic Instructions 52865f3bb9SMichael Rolnik# 53865f3bb9SMichael RolnikADD 0000 11 . ..... .... @op_rd_rr 54865f3bb9SMichael RolnikADC 0001 11 . ..... .... @op_rd_rr 55865f3bb9SMichael RolnikADIW 1001 0110 .. .. .... @op_rd_imm6 56865f3bb9SMichael RolnikSUB 0001 10 . ..... .... @op_rd_rr 57865f3bb9SMichael RolnikSUBI 0101 .... .... .... @op_rd_imm8 58865f3bb9SMichael RolnikSBC 0000 10 . ..... .... @op_rd_rr 59865f3bb9SMichael RolnikSBCI 0100 .... .... .... @op_rd_imm8 60865f3bb9SMichael RolnikSBIW 1001 0111 .. .. .... @op_rd_imm6 61865f3bb9SMichael RolnikAND 0010 00 . ..... .... @op_rd_rr 62865f3bb9SMichael RolnikANDI 0111 .... .... .... @op_rd_imm8 63865f3bb9SMichael RolnikOR 0010 10 . ..... .... @op_rd_rr 64865f3bb9SMichael RolnikORI 0110 .... .... .... @op_rd_imm8 65865f3bb9SMichael RolnikEOR 0010 01 . ..... .... @op_rd_rr 66865f3bb9SMichael RolnikCOM 1001 010 rd:5 0000 67865f3bb9SMichael RolnikNEG 1001 010 rd:5 0001 68865f3bb9SMichael RolnikINC 1001 010 rd:5 0011 69865f3bb9SMichael RolnikDEC 1001 010 rd:5 1010 70865f3bb9SMichael RolnikMUL 1001 11 . ..... .... @op_rd_rr 71865f3bb9SMichael RolnikMULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a 72865f3bb9SMichael RolnikMULSU 0000 0011 0 ... 0 ... @fmul 73865f3bb9SMichael RolnikFMUL 0000 0011 0 ... 1 ... @fmul 74865f3bb9SMichael RolnikFMULS 0000 0011 1 ... 0 ... @fmul 75865f3bb9SMichael RolnikFMULSU 0000 0011 1 ... 1 ... @fmul 76865f3bb9SMichael RolnikDES 1001 0100 imm:4 1011 779d316c75SMichael Rolnik 789d316c75SMichael Rolnik# 799d316c75SMichael Rolnik# Branch Instructions 809d316c75SMichael Rolnik# 819d316c75SMichael Rolnik 829d316c75SMichael Rolnik# The 22-bit immediate is partially in the opcode word, 839d316c75SMichael Rolnik# and partially in the next. Use append_16 to build the 849d316c75SMichael Rolnik# complete 22-bit value. 859d316c75SMichael Rolnik%imm_call 4:5 0:1 !function=append_16 869d316c75SMichael Rolnik 879d316c75SMichael Rolnik@op_bit .... .... . bit:3 .... 889d316c75SMichael Rolnik@op_bit_imm .... .. imm:s7 bit:3 899d316c75SMichael Rolnik 909d316c75SMichael RolnikRJMP 1100 imm:s12 919d316c75SMichael RolnikIJMP 1001 0100 0000 1001 929d316c75SMichael RolnikEIJMP 1001 0100 0001 1001 939d316c75SMichael RolnikJMP 1001 010 ..... 110 . imm=%imm_call 949d316c75SMichael RolnikRCALL 1101 imm:s12 959d316c75SMichael RolnikICALL 1001 0101 0000 1001 969d316c75SMichael RolnikEICALL 1001 0101 0001 1001 979d316c75SMichael RolnikCALL 1001 010 ..... 111 . imm=%imm_call 989d316c75SMichael RolnikRET 1001 0101 0000 1000 999d316c75SMichael RolnikRETI 1001 0101 0001 1000 1009d316c75SMichael RolnikCPSE 0001 00 . ..... .... @op_rd_rr 1019d316c75SMichael RolnikCP 0001 01 . ..... .... @op_rd_rr 1029d316c75SMichael RolnikCPC 0000 01 . ..... .... @op_rd_rr 1039d316c75SMichael RolnikCPI 0011 .... .... .... @op_rd_imm8 1049d316c75SMichael RolnikSBRC 1111 110 rr:5 0 bit:3 1059d316c75SMichael RolnikSBRS 1111 111 rr:5 0 bit:3 1069d316c75SMichael RolnikSBIC 1001 1001 reg:5 bit:3 1079d316c75SMichael RolnikSBIS 1001 1011 reg:5 bit:3 1089d316c75SMichael RolnikBRBS 1111 00 ....... ... @op_bit_imm 1099d316c75SMichael RolnikBRBC 1111 01 ....... ... @op_bit_imm 1109732b024SMichael Rolnik 1119732b024SMichael Rolnik# 1129732b024SMichael Rolnik# Data Transfer Instructions 1139732b024SMichael Rolnik# 1149732b024SMichael Rolnik 1159732b024SMichael Rolnik%rd_d 4:4 !function=to_regs_00_30_by_two 1169732b024SMichael Rolnik%rr_d 0:4 !function=to_regs_00_30_by_two 1179732b024SMichael Rolnik 1189732b024SMichael Rolnik@io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm 1199732b024SMichael Rolnik@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm 1209732b024SMichael Rolnik 1219732b024SMichael Rolnik# The 16-bit immediate is completely in the next word. 1229732b024SMichael Rolnik# Fields cannot be defined with no bits, so we cannot play 1239732b024SMichael Rolnik# the same trick and append to a zero-bit value. 1249732b024SMichael Rolnik# Defer reading the immediate until trans_{LDS,STS}. 1259732b024SMichael Rolnik@ldst_s .... ... rd:5 .... imm=0 1269732b024SMichael Rolnik 1279732b024SMichael RolnikMOV 0010 11 . ..... .... @op_rd_rr 1289732b024SMichael RolnikMOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d 1299732b024SMichael RolnikLDI 1110 .... .... .... @op_rd_imm8 1309732b024SMichael RolnikLDS 1001 000 ..... 0000 @ldst_s 1319732b024SMichael RolnikLDX1 1001 000 rd:5 1100 1329732b024SMichael RolnikLDX2 1001 000 rd:5 1101 1339732b024SMichael RolnikLDX3 1001 000 rd:5 1110 1349732b024SMichael RolnikLDY2 1001 000 rd:5 1001 1359732b024SMichael RolnikLDY3 1001 000 rd:5 1010 1369732b024SMichael RolnikLDZ2 1001 000 rd:5 0001 1379732b024SMichael RolnikLDZ3 1001 000 rd:5 0010 1389732b024SMichael RolnikLDDY 10 . 0 .. 0 ..... 1 ... @ldst_d 1399732b024SMichael RolnikLDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d 1409732b024SMichael RolnikSTS 1001 001 ..... 0000 @ldst_s 1419732b024SMichael RolnikSTX1 1001 001 rr:5 1100 1429732b024SMichael RolnikSTX2 1001 001 rr:5 1101 1439732b024SMichael RolnikSTX3 1001 001 rr:5 1110 1449732b024SMichael RolnikSTY2 1001 001 rd:5 1001 1459732b024SMichael RolnikSTY3 1001 001 rd:5 1010 1469732b024SMichael RolnikSTZ2 1001 001 rd:5 0001 1479732b024SMichael RolnikSTZ3 1001 001 rd:5 0010 1489732b024SMichael RolnikSTDY 10 . 0 .. 1 ..... 1 ... @ldst_d 1499732b024SMichael RolnikSTDZ 10 . 0 .. 1 ..... 0 ... @ldst_d 1509732b024SMichael RolnikLPM1 1001 0101 1100 1000 1519732b024SMichael RolnikLPM2 1001 000 rd:5 0100 1529732b024SMichael RolnikLPMX 1001 000 rd:5 0101 1539732b024SMichael RolnikELPM1 1001 0101 1101 1000 1549732b024SMichael RolnikELPM2 1001 000 rd:5 0110 1559732b024SMichael RolnikELPMX 1001 000 rd:5 0111 1569732b024SMichael RolnikSPM 1001 0101 1110 1000 1579732b024SMichael RolnikSPMX 1001 0101 1111 1000 1589732b024SMichael RolnikIN 1011 0 .. ..... .... @io_rd_imm 1599732b024SMichael RolnikOUT 1011 1 .. ..... .... @io_rd_imm 1609732b024SMichael RolnikPUSH 1001 001 rd:5 1111 1619732b024SMichael RolnikPOP 1001 000 rd:5 1111 1629732b024SMichael RolnikXCH 1001 001 rd:5 0100 1639732b024SMichael RolnikLAC 1001 001 rd:5 0110 1649732b024SMichael RolnikLAS 1001 001 rd:5 0101 1659732b024SMichael RolnikLAT 1001 001 rd:5 0111 1665718cef0SMichael Rolnik 1675718cef0SMichael Rolnik# 1685718cef0SMichael Rolnik# Bit and Bit-test Instructions 1695718cef0SMichael Rolnik# 1705718cef0SMichael RolnikLSR 1001 010 rd:5 0110 1715718cef0SMichael RolnikROR 1001 010 rd:5 0111 1725718cef0SMichael RolnikASR 1001 010 rd:5 0101 1735718cef0SMichael RolnikSWAP 1001 010 rd:5 0010 1745718cef0SMichael RolnikSBI 1001 1010 reg:5 bit:3 1755718cef0SMichael RolnikCBI 1001 1000 reg:5 bit:3 1765718cef0SMichael RolnikBST 1111 101 rd:5 0 bit:3 1775718cef0SMichael RolnikBLD 1111 100 rd:5 0 bit:3 1785718cef0SMichael RolnikBSET 1001 0100 0 bit:3 1000 1795718cef0SMichael RolnikBCLR 1001 0100 1 bit:3 1000 180*46188cabSMichael Rolnik 181*46188cabSMichael Rolnik# 182*46188cabSMichael Rolnik# MCU Control Instructions 183*46188cabSMichael Rolnik# 184*46188cabSMichael RolnikBREAK 1001 0101 1001 1000 185*46188cabSMichael RolnikNOP 0000 0000 0000 0000 186*46188cabSMichael RolnikSLEEP 1001 0101 1000 1000 187*46188cabSMichael RolnikWDR 1001 0101 1010 1000 188