Merge tag 'single-binary-20241015' of https://github.com/philmd/qemu into staging

Remove some target-specific endianness knowledge from target/.

For MIPS, propagate endianness at the board level, u

Merge tag 'single-binary-20241015' of https://github.com/philmd/qemu into staging

Remove some target-specific endianness knowledge from target/.

For MIPS, propagate endianness at the board level, using QOM property.

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcOihcACgkQ4+MsLN6t
# wN4VaRAAor+5gUJiV0OOMQVfP8e1o9ssKcYy9m31zLeii1Iq2M/2oz6YK4OjdQDe
# oJ8VRJvBPKC2Bpi14TfKsSGaP8CGNO/hdxcMi71pjHZC+bjHt5Uv0U/7T4XCBWuV
# N+85juN1PTc4cci4FkGIXaPB1YWL00L56BDCzja0uhLF4+Xe2eYGVrPXeFCkN/3I
# Ky7jHlB/dgzc47kTXvg5snCee2egDFf/x4igwZj6+gWJyo+jubRpwoOqKbK2M0Nd
# VvNpBVFNGZMP3Fn9lh45uDOuRWGu6zSIPBVkjoFc+wdGsFsITIMrZ3h46UffsGTJ
# F1j6Zsq6hoLbaNRRjZ6OsN6u683oo1lknmWauD62LrjXcX0RlRwRFbMD0AjedR8t
# 6+YHg5LlwGg6r/AOtEe28ggXZohB2vjr2V0MJm1x/XgLYhFHoN3//jxn22oOHj4p
# 0z3+eDc3Se8JNRV6jPMHbbuTqZqZjRgVFbYN3aMbdoXYzhpYnrPj6f7WQL2smiAW
# C2vdswrubQWKou1wcn6rbg0nnMRVTh+GxrtZ3mkgaxNzgNFxsrX8YubMsh77XUcr
# mnCGj1tE3hp40xsuSk6yZXY3ZZiTyZasvO1wq4gWOI9le0Zmq+d335F9+IVJ8RlP
# YhA+MY5aeomsixVRdmrPrgOfanQiHXv02lsbperU8QFfGRhf2Y8=
# =Qydb
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 15 Oct 2024 16:28:23 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* tag 'single-binary-20241015' of https://github.com/philmd/qemu: (33 commits)
hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
hw/mips/cps: Set the vCPU 'cpu-big-endian' property
target/mips: Expose MIPSCPU::is_big_endian property
target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
target/mips: Use gen_op_addr_addi() when possible
target/mips: Have gen_addiupc() expand $pc during translation
target/mips: Replace MO_TE by mo_endian()
target/mips: Introduce mo_endian() helper
target/mips: Remove unused MEMOP_IDX() macro
target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()
target/mips: Explode MO_TExx -> MO_TE | MO_xx
target/mips: Factor mo_endian_rev() out of MXU code
target/mips: Convert mips16e decr_and_load/store() macros to functions
target/mips: Replace MO_TE by mo_endian_env() in get_pte()
target/mips: Introduce mo_endian_env() helper
target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()
target/mips: Declare mips_env_is_bigendian() in 'internal.h'
hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry
target/ppc: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/mips: Replace MO_TE by mo_endian()

Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.

Mechanical change using:

$ sed -i -e

target/mips: Replace MO_TE by mo_endian()

Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.

Mechanical change using:

$ sed -i -e 's/MO_TE/mo_endian(ctx)/' \
$(git grep -l MO_TE target/mips)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-11-philmd@linaro.org>

show more ...

target/mips: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.

Mechanical change using:

$ for n in UW UL UQ UO

target/mips: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.

Mechanical change using:

$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/mips); \
done

manually remove superfluous parenthesis in nanoMIPS gen_save().

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-8-philmd@linaro.org>

show more ...

Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging

Build tcg/ once for system and once for user.
Unmap perf_marker.
Remove left over _link_error() definitions.

# -----BEG

Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging

Build tcg/ once for system and once for user.
Unmap perf_marker.
Remove left over _link_error() definitions.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmR+QekdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8NJwf+PE6ShfN+N65hwt0w
# mgIrWNadgnXezEyaUdEuzLre9Ln9uD9Are948xIGPTVoLyr2wEr+Ma9dFI+GpTHY
# 8C0b5v0SfHBBIK+wJb7VNcEdssRXVTcpikmmYv9IRpFTT8349bCdvJhuwojU5cyx
# NGgq9ydJ/dEUDtmVU6EnOyLCDSHg2mc+KPVWhjXaVbVPTyP6Xmb0BwSSUt1t5NQK
# Zw7E6G4z7QYXa7GNPTtXSWzTH3y9bSLQNj3jzHfJ6DPW23zxhFjCPhJYl1ecOHVF
# pxXEEIjieHQxdlm3kg+tcCoZSJ6OXESNzu2D8zk8Kf6xJjMItTQOOuokWM6mBX4y
# VbQoXg==
# =8vrl
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 05 Jun 2023 01:13:29 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu: (52 commits)
tcg/tcg-op-vec: Remove left over _link_error() definitions
accel/tcg: Unmap perf_marker
tcg: Build once for system and once for user-only
exec/poison: Do not poison CONFIG_SOFTMMU
plugins: Drop unused headers from exec/plugin-gen.h
plugins: Move plugin_insn_append to translator.c
tcg: Remove target-specific headers from tcg.[ch]
tcg: Move env defines out of NEED_CPU_H in helper-head.h
tcg: Fix PAGE/PROT confusion
accel/tcg: Tidy includes for translator.[ch]
target/arm: Add missing include of exec/exec-all.h
target/*: Add missing includes of exec/translation-block.h
target/mips: Tidy helpers for translation
target/arm: Tidy helpers for translation
accel/tcg: Move translator_fake_ldb out of line
target/ppc: Inline gen_icount_io_start()
accel/tcg: Introduce translator_io_start
accel/tcg: Move most of gen-icount.h into translator.c
include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE
tcg: Spit out exec/translation-block.h
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/mips: Tidy helpers for translation

Move most includes from *translate*.c to translate.h, ensuring
that we get the ordering correct. Ensure cpu.h is first.
Use disas/disas.h instead of exec/l

target/mips: Tidy helpers for translation

Move most includes from *translate*.c to translate.h, ensuring
that we get the ordering correct. Ensure cpu.h is first.
Use disas/disas.h instead of exec/log.h.
Drop otherwise unused includes.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/

Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging

accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQPcb0dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV885AgAjDbg1soRBy0THf0X
# CVXmQ4yYyUKAonZBL8Abt9yX01BhLFqEsrju3HiaLNOM9DbwWQ4gdvSrtAZ/K2YG
# d6EvC+rJe79pr58MEEhqO4OO1ymp52amRHtEXva4vcKRNuM9WF5by/Hz2PsZyenG
# ysaLBdddooA9SJeL7xYBMpKWFgUm3C8NzfaRfCBVcG94er9u8RUi0kx+drmOLw0g
# vZ3Hekvi2I8Y5mWqvHeAIOsr8Md9PO3ezWxEteE4qsPNTTRfVD93oSGe9nNCYZTX
# wWU51Vfv9GB6hOylAfMRIeCmkjks/gqLOGElsh1MaVovNDTXS5IKV/HgaLaocJHV
# 2P81uQ==
# =FpIY
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 13 Mar 2023 18:55:57 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits)
tcg: Drop tcg_const_*
tcg: Drop tcg_const_*_vec
target/tricore: Use min/max for saturate
target/ppc: Avoid tcg_const_* in translate.c
target/ppc: Fix gen_tlbsx_booke206
target/ppc: Rewrite trans_ADDG6S
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
target/ppc: Avoid tcg_const_* in xxeval
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
target/ppc: Avoid tcg_const_i64 in do_vcntmb
target/m68k: Use tcg_constant_i32 in gen_ea_mode
target/arm: Avoid tcg_const_ptr in handle_rev
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
target/arm: Avoid tcg_const_* in translate-mve.c
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
target/arm: Improve trans_BFCI
target/arm: Create gen_set_rmode, gen_restore_rmode
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/mips: Avoid tcg_const_* throughout

All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@lina

target/mips: Avoid tcg_const_* throughout

All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/mips: Drop tcg_temp_free from tx79_translate.c

Translators are no longer required to free tcg temporaries.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Hend

target/mips: Drop tcg_temp_free from tx79_translate.c

Translators are no longer required to free tcg temporaries.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- Si

Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions

# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

exec/memop: Adding signedness to quad definitions

Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit

exec/memop: Adding signedness to quad definitions

Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
-

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
- converted NEC Vr54xx extension opcodes to decodetree
- housekeeping in gen_helper() macros
- replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
- allow Loongson 3A1000 to use up to 48-bit VAddr

# gpg: Signature made Wed 25 Aug 2021 12:04:31 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210825: (28 commits)
target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()
target/mips: Store CP0_Config0 in DisasContext
target/mips: Replace GET_LMASK64() macro by get_lmask(64) function
target/mips: Replace GET_LMASK() macro by get_lmask(32) function
target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers
target/mips: Define gen_helper() macros in translate.h
target/mips: Use tcg_constant_i32() in generate_exception_err()
target/mips: Inline gen_helper_0e0i()
target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros
target/mips: Simplify gen_helper() macros by using tcg_constant_i32()
target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
target/mips: Remove gen_helper_1e2i()
target/mips: Remove gen_helper_0e3i()
target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
target/mips: Document Loongson-3A CPU definitions
target/mips: Convert Vr54xx MSA* opcodes to decodetree
target/mips: Convert Vr54xx MUL* opcodes to decodetree
target/mips: Convert Vr54xx MACC* opcodes to decodetree
target/mips: Introduce decodetree structure for NEC Vr54xx extension
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/mips: Rename 'rtype' as 'r'

We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes

target/mips: Rename 'rtype' as 'r'

We'll soon have more opcode and decoded arguments, and 'rtype'
is not very helpful. Naming it simply 'r' ease reviewing the
.decode files when we have many opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-5-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging

MIPS patches queue

- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes imple

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging

MIPS patches queue

- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes implemented
- Rewrite UHI errno_mips() using switch statement
- Few fixes and improvements in the SONIC model (dp8393x)

# gpg: Signature made Sun 11 Jul 2021 22:12:49 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210711:
dp8393x: don't force 32-bit register access
dp8393x: Rewrite dp8393x_get() / dp8393x_put()
dp8393x: Store CAM registers as 16-bit
dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition
dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
dp8393x: fix CAM descriptor entry index
target/mips: Rewrite UHI errno_mips() using switch statement
target/mips/tx79: Introduce SQ opcode (Store Quadword)
target/mips/tx79: Introduce LQ opcode (Load Quadword)
target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)
hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/mips/tx79: Introduce SQ opcode (Store Quadword)

Introduce the SQ opcode (Store Quadword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.hend

target/mips/tx79: Introduce SQ opcode (Store Quadword)

Introduce the SQ opcode (Store Quadword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-27-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce LQ opcode (Load Quadword)

Introduce the LQ opcode (Load Quadword) and remove unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richa

target/mips/tx79: Introduce LQ opcode (Load Quadword)

Introduce the LQ opcode (Load Quadword) and remove unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-26-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)

Introduce the PROT3W opcode (Parallel Rotate 3 Words).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richa

target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)

Introduce the PROT3W opcode (Parallel Rotate 3 Words).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-25-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)

Introduce the PPACW opcode (Parallel Pack to Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Hen

target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)

Introduce the PPACW opcode (Parallel Pack to Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-22-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)

Introduce the 'Parallel Compare for Greater Than' opcodes:

- PCGTB (Parallel Compare for Greater Than Byte)
- PCGTH (Parallel

target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)

Introduce the 'Parallel Compare for Greater Than' opcodes:

- PCGTB (Parallel Compare for Greater Than Byte)
- PCGTH (Parallel Compare for Greater Than Halfword)
- PCGTW (Parallel Compare for Greater Than Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-15-f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)

Introduce the 'Parallel Compare for Equal' opcodes:

- PCEQB (Parallel Compare for Equal Byte)
- PCEQH (Parallel Compare for

target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)

Introduce the 'Parallel Compare for Equal' opcodes:

- PCEQB (Parallel Compare for Equal Byte)
- PCEQH (Parallel Compare for Equal Halfword)
- PCEQW (Parallel Compare for Equal Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-14-f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)

Introduce the 'Parallel Extend Lower' opcodes:

- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper fr

target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)

Introduce the 'Parallel Extend Lower' opcodes:

- PEXTLB (Parallel Extend Upper from Byte)
- PEXTLH (Parallel Extend Upper from Halfword)
- PEXTLW (Parallel Extend Upper from Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-13-f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

Introduce the PEXTUW opcode (Parallel Extend Upper from Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-

target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

Introduce the PEXTUW opcode (Parallel Extend Upper from Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-12-f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)

Introduce the 'Parallel Subtract' opcodes:

- PSUBB (Parallel Subtract Byte)
- PSUBH (Parallel Subtract Halfword)
- PSUBW (Parallel S

target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)

Introduce the 'Parallel Subtract' opcodes:

- PSUBB (Parallel Subtract Byte)
- PSUBH (Parallel Subtract Halfword)
- PSUBW (Parallel Subtract Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <820210309145653.743937-11-f4bug@amsat.org>

show more ...

target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)

Introduce the parallel logic opcodes:

- PAND (Parallel AND)
- POR (Parallel OR)
- PXOR (Parallel XOR)
- PNOR (Parallel N

target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)

Introduce the parallel logic opcodes:

- PAND (Parallel AND)
- POR (Parallel OR)
- PXOR (Parallel XOR)
- PNOR (Parallel NOR)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-16-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging

MIPS patches queue

- Fix CACHEE opcode
- Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
- Remove isa_get_ir

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging

MIPS patches queue

- Fix CACHEE opcode
- Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
- Remove isa_get_irq() call in PIIX4 south bridge
- Add various missing fields to the MIPS CPU migration vmstate
- Lot of code moved around to allow TCG or KVM only builds
- Restrict non-virtualized machines to TCG
- Add KVM mips64el cross-build jobs to gitlab-ci

# gpg: Signature made Sun 02 May 2021 15:56:51 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210502: (36 commits)
gitlab-ci: Add KVM mips64el cross-build jobs
hw/mips: Restrict non-virtualized machines to TCG
target/mips: Move TCG source files under tcg/ sub directory
target/mips: Move CP0 helpers to sysemu/cp0.c
target/mips: Move exception management code to exception.c
target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
target/mips: Move tlb_helper.c to tcg/sysemu/
target/mips: Restrict mmu_init() to TCG
target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
target/mips: Move physical addressing code to sysemu/physaddr.c
target/mips: Move sysemu specific files under sysemu/ subfolder
target/mips: Move cpu_signal_handler definition around
target/mips: Add simple user-mode mips_cpu_tlb_fill()
target/mips: Add simple user-mode mips_cpu_do_interrupt()
target/mips: Introduce tcg-internal.h for TCG specific declarations
meson: Introduce meson_user_arch source set for arch-specific user-mode
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/mips: Move TCG source files under tcg/ sub directory

To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.

The following prototypes:
- mip

target/mips: Move TCG source files under tcg/ sub directory

To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.

The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-29-f4bug@amsat.org>

show more ...