1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 291a9fec0SRob Herring/* 391a9fec0SRob Herring * arch/arm/include/debug/icedcc.S 491a9fec0SRob Herring * 591a9fec0SRob Herring * Copyright (C) 1994-1999 Russell King 691a9fec0SRob Herring */ 791a9fec0SRob Herring 891a9fec0SRob Herring @@ debug using ARM EmbeddedICE DCC channel 991a9fec0SRob Herring 1091a9fec0SRob Herring .macro addruart, rp, rv, tmp 1191a9fec0SRob Herring .endm 1291a9fec0SRob Herring 1391a9fec0SRob Herring#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) 1491a9fec0SRob Herring 1591a9fec0SRob Herring .macro senduart, rd, rx 1691a9fec0SRob Herring mcr p14, 0, \rd, c0, c5, 0 1791a9fec0SRob Herring .endm 1891a9fec0SRob Herring 1991a9fec0SRob Herring .macro busyuart, rd, rx 2091a9fec0SRob Herring1001: 2191a9fec0SRob Herring mrc p14, 0, \rx, c0, c1, 0 2291a9fec0SRob Herring tst \rx, #0x20000000 2391a9fec0SRob Herring beq 1001b 2491a9fec0SRob Herring .endm 2591a9fec0SRob Herring 26*2c50a570SLinus Walleij .macro waituartcts, rd, rx 27*2c50a570SLinus Walleij .endm 28*2c50a570SLinus Walleij 29*2c50a570SLinus Walleij .macro waituarttxrdy, rd, rx 3091a9fec0SRob Herring mov \rd, #0x2000000 3191a9fec0SRob Herring1001: 3291a9fec0SRob Herring subs \rd, \rd, #1 3391a9fec0SRob Herring bmi 1002f 3491a9fec0SRob Herring mrc p14, 0, \rx, c0, c1, 0 3591a9fec0SRob Herring tst \rx, #0x20000000 3691a9fec0SRob Herring bne 1001b 3791a9fec0SRob Herring1002: 3891a9fec0SRob Herring .endm 3991a9fec0SRob Herring 4091a9fec0SRob Herring#elif defined(CONFIG_CPU_XSCALE) 4191a9fec0SRob Herring 4291a9fec0SRob Herring .macro senduart, rd, rx 4391a9fec0SRob Herring mcr p14, 0, \rd, c8, c0, 0 4491a9fec0SRob Herring .endm 4591a9fec0SRob Herring 4691a9fec0SRob Herring .macro busyuart, rd, rx 4791a9fec0SRob Herring1001: 4891a9fec0SRob Herring mrc p14, 0, \rx, c14, c0, 0 4991a9fec0SRob Herring tst \rx, #0x10000000 5091a9fec0SRob Herring beq 1001b 5191a9fec0SRob Herring .endm 5291a9fec0SRob Herring 53*2c50a570SLinus Walleij .macro waituartcts, rd, rx 54*2c50a570SLinus Walleij .endm 55*2c50a570SLinus Walleij 56*2c50a570SLinus Walleij .macro waituarttxrdy, rd, rx 5791a9fec0SRob Herring mov \rd, #0x10000000 5891a9fec0SRob Herring1001: 5991a9fec0SRob Herring subs \rd, \rd, #1 6091a9fec0SRob Herring bmi 1002f 6191a9fec0SRob Herring mrc p14, 0, \rx, c14, c0, 0 6291a9fec0SRob Herring tst \rx, #0x10000000 6391a9fec0SRob Herring bne 1001b 6491a9fec0SRob Herring1002: 6591a9fec0SRob Herring .endm 6691a9fec0SRob Herring 6791a9fec0SRob Herring#else 6891a9fec0SRob Herring 6991a9fec0SRob Herring .macro senduart, rd, rx 7091a9fec0SRob Herring mcr p14, 0, \rd, c1, c0, 0 7191a9fec0SRob Herring .endm 7291a9fec0SRob Herring 7391a9fec0SRob Herring .macro busyuart, rd, rx 7491a9fec0SRob Herring1001: 7591a9fec0SRob Herring mrc p14, 0, \rx, c0, c0, 0 7691a9fec0SRob Herring tst \rx, #2 7791a9fec0SRob Herring beq 1001b 7891a9fec0SRob Herring 7991a9fec0SRob Herring .endm 8091a9fec0SRob Herring 81*2c50a570SLinus Walleij .macro waituartcts, rd, rx 82*2c50a570SLinus Walleij .endm 83*2c50a570SLinus Walleij 84*2c50a570SLinus Walleij .macro waituarttxrdy, rd, rx 8591a9fec0SRob Herring mov \rd, #0x2000000 8691a9fec0SRob Herring1001: 8791a9fec0SRob Herring subs \rd, \rd, #1 8891a9fec0SRob Herring bmi 1002f 8991a9fec0SRob Herring mrc p14, 0, \rx, c0, c0, 0 9091a9fec0SRob Herring tst \rx, #2 9191a9fec0SRob Herring bne 1001b 9291a9fec0SRob Herring1002: 9391a9fec0SRob Herring .endm 9491a9fec0SRob Herring 9591a9fec0SRob Herring#endif /* CONFIG_CPU_V6 */ 96