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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,xps-spi-2.00.a
19 - xlnx,xps-spi-2.00.b
20 - xlnx,axi-quad-spi-1.00.a
28 xlnx,num-ss-bits:
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/openbmc/linux/drivers/spi/
H A Dspi-topcliff-pch.c1 // SPDX-License-Identifier: GPL-2.0-only
79 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
124 * struct pch_spi_data - Holds the SPI channel specific details
131 * @transfer_complete: Status of SPI Transfer
136 * @bpw_len: Length of data to be transferred in bits per
138 * @transfer_active: Flag showing active transfer
140 * transfer
142 * transfer
151 * @cur_trans: The current transfer that this SPI driver is
192 * struct pch_spi_board_data - Holds the SPI device specific details
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/openbmc/linux/sound/core/
H A Dpcm_lib.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Abramo Bagnara <abramo@alsa-project.org>
43 delta = new_ptr - ptr; in update_silence_vars()
47 delta += runtime->boundary; in update_silence_vars()
48 if ((snd_pcm_uframes_t)delta < runtime->silence_filled) in update_silence_vars()
49 runtime->silence_filled -= delta; in update_silence_vars()
51 runtime->silence_filled = 0; in update_silence_vars()
52 runtime->silence_start = new_ptr; in update_silence_vars()
57 * runtime->silence_start: starting pointer to silence area
58 * runtime->silence_filled: size filled with silence
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/openbmc/linux/drivers/media/common/saa7146/
H A Dsaa7146_i2c.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <media/drv-intf/saa7146_vv.h>
8 /* DEB_I2C("'%s'\n", adapter->name); */ in saa7146_i2c_func()
16 /* this function returns the status-register of our i2c-device */
24 /* this function runs through the i2c-messages and prepares the data to be
26 to understand this. it returns the number of u32s to send, or -1
28 static int saa7146_i2c_msg_prepare(const struct i2c_msg *m, int num, __le32 *op) in saa7146_i2c_msg_prepare() argument
35 for(i = 0; i < num; i++) { in saa7146_i2c_msg_prepare()
41 mem = 1 + ((mem-1) / 3); in saa7146_i2c_msg_prepare()
47 /* DEB_I2C("cannot prepare i2c-message\n"); */ in saa7146_i2c_msg_prepare()
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-stm32f4.c1 // SPDX-License-Identifier: GPL-2.0
13 * This driver is based on i2c-st.c
31 #include "i2c-stm32.h"
97 * struct stm32f4_i2c_msg - client specific data
98 * @addr: 8-bit slave addr, including r/w bit
101 * @result: result of the transfer
113 * struct stm32f4_i2c_dev - private data of the controller
121 * @msg: I2C transfer information
146 void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2; in stm32f4_i2c_disable_irq()
156 i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk); in stm32f4_i2c_set_periph_clk_freq()
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H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
36 #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
39 #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
76 /* calculate the value of CS bits in CCR register on standard mode */
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
81 /* calculate the value of CS bits in CSR register on standard mode */
84 /* calculate the value of CS bits in CCR register on fast mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
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H A Di2c-axxia.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * maximum 255 bytes at a time. If a larger transfer is attempted, error code
8 * (-EINVAL) is returned.
84 #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */
86 #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */
106 #define SLV_STATUS_WTC BIT(1) /* Write transfer complete */
121 * struct axxia_i2c_dev - I2C device context
124 * @msg_r: pointer to current read message (sequence transfer)
133 * @last: a flag indicating is this is last message in transfer
156 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_disable()
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H A Di2c-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 * data register whereas STB SoCs use 4 byte per data register transfer,
52 /* Condition mask used for non combined transfer */
58 /* BSC data transfer direction */
61 /* BSC data transfer direction combined format */
175 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
178 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
182 return (N_DATA_REGS * dev->data_regsz); in brcmstb_i2c_get_xfersz()
187 return dev->data_regsz; in brcmstb_i2c_get_data_regsz()
196 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; in brcmstb_i2c_enable_disable_irq()
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H A Di2c-meson.c1 // SPDX-License-Identifier: GPL-2.0-only
68 * struct meson_i2c - Meson I2C device private data
76 * @last: Flag set for the last message in the transfer
77 * @count: Number of bytes to be sent/received in current transfer
81 * @done: Completion used to wait for transfer termination
116 data = readl(i2c->regs + reg); in meson_i2c_set_mask()
119 writel(data, i2c->regs + reg); in meson_i2c_set_mask()
124 i2c->tokens[0] = 0; in meson_i2c_reset_tokens()
125 i2c->tokens[1] = 0; in meson_i2c_reset_tokens()
126 i2c->num_tokens = 0; in meson_i2c_reset_tokens()
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H A Di2c-qup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
126 /* Maximum transfer length for single DMA descriptor */
129 /* Maximum transfer length for all DMA descriptors */
134 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
135 * the top of maximum transfer time calculated from i2c bus speed to compensate
146 * data transfer
167 * total_tx_len: total tx length including tag bytes for current QUP transfer
168 * total_rx_len: total rx length including tag bytes for current QUP transfer
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H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
27 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */
38 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
61 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
62 * bits. A write access to this register always initiates a transfer if the I2C
120 /* Transfer size in multiples of data interrupt depth */
121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)
123 #define DRIVER_NAME "cdns-i2c"
134 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
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H A Di2c-pnx.c7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
82 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
83 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
84 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
85 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
86 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
87 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
88 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
89 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
90 #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
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H A Di2c-exynos5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
32 * Special bits are available for both modes of operation to set commands
33 * and for checking transfer status
62 /* I2C_CTL Register bits */
69 /* I2C_FIFO_CTL Register bits */
75 /* I2C_TRAILING_CTL Register bits */
78 /* I2C_INT_EN Register bits */
83 /* I2C_INT_STAT Register bits */
104 /* I2C_FIFO_STAT Register bits */
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/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
28 * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz in fifo_transfer()
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
44 * Limit transfer length by FIFO threshold or FIFO size. in fifo_transfer()
49 /* Wait until error, FIFO request bit set or transfer complete */ in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
59 ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
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/openbmc/linux/drivers/usb/gadget/udc/bdc/
H A Dbdc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * bdc.h - header for the BRCM BDC USB3.0 device controller
18 #include <linux/dma-mapping.h>
46 /* Num of bds per table */
49 /* Num of tables in bd list for control,bulk and Int ep */
52 /* Num of tables in bd list for Isoch ep */
223 /* Control transfer BD specific fields */
242 /* Transfer BD fields */
252 /* One BD can transfer max 65536 bytes */
274 /* On disconnect, preserve these bits and clear rest */
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/openbmc/linux/drivers/message/fusion/
H A Dmptctl.h8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
54 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
93 * (as the app. will not use 8-byte pointers).
117 * iocnum - must be defined.
118 * port - must be defined for all IOCTL commands other than MPTIOCINFO
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/openbmc/qemu/docs/interop/
H A Dvhost-user.rst4 Vhost-user Protocol
11 version 2 or later. See the COPYING file in the top-level
26 The protocol defines 2 sides of the communication, *front-end* and
27 *back-end*. The *front-end* is the application that shares its virtqueues, in
28 our case QEMU. The *back-end* is the consumer of the virtqueues.
30 In the current implementation QEMU is the *front-end*, and the *back-end*
33 or a block device back-end processing read & write to a virtual
34 disk. In order to facilitate interoperability between various back-end
38 The *front-end* and *back-end* can be either a client (i.e. connecting) or
42 --------------------------------------
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/openbmc/linux/drivers/mmc/core/
H A Dsdio_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Pierre Ossman
21 * sdio_claim_host - exclusively claim a bus for a certain SDIO function
32 mmc_claim_host(func->card->host); in sdio_claim_host()
37 * sdio_release_host - release a bus for a certain SDIO function
48 mmc_release_host(func->card->host); in sdio_release_host()
53 * sdio_enable_func - enables a SDIO function for usage
66 return -EINVAL; in sdio_enable_func()
70 ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IOEx, 0, &reg); in sdio_enable_func()
74 reg |= 1 << func->num; in sdio_enable_func()
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/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
24 check the status of each of the bits of this register independently. The use
25 of 32 bits per interrupt line enables software to provide more information
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
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/openbmc/linux/drivers/usb/gadget/udc/cdns2/
H A Dcdns2-gadget.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence USBHS-DEV Driver - gadget side.
28 #include <linux/dma-mapping.h>
35 #include "cdns2-gadget.h"
36 #include "cdns2-trace.h"
39 * set_reg_bit_32 - set bit in given 32 bits register.
41 * @mask: bits to set.
50 * clear_reg_bit_32 - clear bit in given 32 bits register.
52 * @mask: bits to clear.
60 /* Clear bit in given 8 bits register. */
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/openbmc/linux/drivers/gpu/drm/
H A Ddrm_mipi_dbi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 * 1. 9-bit with the Data/Command signal as the ninth bit
63 * 2. Same as above except it's sent as 16 bits
64 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
108 if (!dbi->read_commands) in mipi_dbi_command_is_read()
112 if (!dbi->read_commands[i]) in mipi_dbi_command_is_read()
114 if (cmd == dbi->read_commands[i]) in mipi_dbi_command_is_read()
122 * mipi_dbi_command_read - MIPI DCS read command
134 if (!dbi->read_commands) in mipi_dbi_command_read()
135 return -EACCES; in mipi_dbi_command_read()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dxor.c1 // SPDX-License-Identifier: GPL-2.0
34 for (ui = 0; ui < (dram_info->num_cs + 1); ui++) { in mv_sys_xor_init()
43 /* Last window - Base - 0x40000000, Attribute 0x1E - SRAM */ in mv_sys_xor_init()
45 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init()
46 /* Last window - Size - 64 MB */ in mv_sys_xor_init()
47 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init()
51 if (dram_info->cs_ena & (1 << ui)) { in mv_sys_xor_init()
53 * Window x - Base - 0x00000000, Attribute 0x0E - DRAM in mv_sys_xor_init()
73 /* Window x - Size - 256 MB */ in mv_sys_xor_init()
98 * mv_xor_hal_init - Initialize XOR engine
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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dxor.c1 // SPDX-License-Identifier: GPL-2.0
54 * window x - Base - 0x00000000, in mv_sys_xor_init()
55 * Attribute 0x0e - DRAM in mv_sys_xor_init()
82 size_mask = (cs_size / _64K) - 1; in mv_sys_xor_init()
84 /* window x - Size */ in mv_sys_xor_init()
110 * mv_xor_hal_init - Initialize XOR engine
137 * mv_xor_ctrl_set - Set XOR channel control registers
171 block_size -= 1; in mv_xor_mem_init()
215 /* start transfer */ in mv_xor_mem_init()
223 * mv_xor_state_get - Get XOR channel state.
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/openbmc/u-boot/drivers/i2c/
H A Dsh_i2c.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Please see doc/driver-model/i2c-howto.txt for instructions.
16 /* Every register is 32bit aligned, but only 8bits in size */
72 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte()
83 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte_with_tack()
85 if (SH_IC_TACK & readb(&dev->icsr)) in sh_irq_dte_with_tack()
86 return -1; in sh_irq_dte_with_tack()
97 if (!(SH_IC_BUSY & readb(&dev->icsr))) in sh_irq_busy()
109 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); in sh_i2c_set_addr()
110 setbits_8(&dev->iccr, SH_I2C_ICCR_ICE); in sh_i2c_set_addr()
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/openbmc/linux/drivers/iio/adc/
H A Dti-adc084s021.c1 // SPDX-License-Identifier: GPL-2.0-only
36 * transfer buffers to live in their own cache line.
39 __be16 rx_buf[5]; /* First 16-bits are trash */
42 #define ADC084S021_VOLTAGE_CHANNEL(num) \ argument
45 .channel = (num), \
47 .scan_index = (num), \
68 * adc084s021_adc_conversion() - Read an ADC channel and return its value.
75 int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */ in adc084s021_adc_conversion()
78 /* Do the transfer */ in adc084s021_adc_conversion()
79 ret = spi_sync(adc->spi, &adc->message); in adc084s021_adc_conversion()
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