1 // SPDX-License-Identifier: GPL-2.0+
7  * Please see doc/driver-model/i2c-howto.txt for instructions.
16 /* Every register is 32bit aligned, but only 8bits in size */
72 		if (SH_IC_DTE & readb(&dev->icsr))  in sh_irq_dte()
83 		if (SH_IC_DTE & readb(&dev->icsr))  in sh_irq_dte_with_tack()
85 		if (SH_IC_TACK & readb(&dev->icsr))  in sh_irq_dte_with_tack()
86 			return -1;  in sh_irq_dte_with_tack()
97 		if (!(SH_IC_BUSY & readb(&dev->icsr)))  in sh_irq_busy()
109 	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);  in sh_i2c_set_addr()
110 	setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);  in sh_i2c_set_addr()
112 	writeb(iccl & 0xff, &dev->iccl);  in sh_i2c_set_addr()
113 	writeb(icch & 0xff, &dev->icch);  in sh_i2c_set_addr()
120 	writeb(icic, &dev->icic);  in sh_i2c_set_addr()
122 	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);  in sh_i2c_set_addr()
125 	clrbits_8(&dev->icsr, SH_IC_TACK);  in sh_i2c_set_addr()
126 	writeb(chip << 1, &dev->icdr);  in sh_i2c_set_addr()
128 		return -1;  in sh_i2c_set_addr()
130 	writeb(addr, &dev->icdr);  in sh_i2c_set_addr()
132 		writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);  in sh_i2c_set_addr()
135 		return -1;  in sh_i2c_set_addr()
141 	writeb(0, &dev->icsr);  in sh_i2c_finish()
142 	clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);  in sh_i2c_finish()
148 	int ret = -1;  in sh_i2c_raw_write()
153 	writeb(val, &dev->icdr);  in sh_i2c_raw_write()
157 	writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);  in sh_i2c_raw_write()
170 	int ret = -1;  in sh_i2c_raw_read()
181 	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);  in sh_i2c_raw_read()
184 	writeb(chip << 1 | 0x01, &dev->icdr);  in sh_i2c_raw_read()
188 	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);  in sh_i2c_raw_read()
192 	ret = readb(&dev->icdr) & 0xff;  in sh_i2c_raw_read()
194 	writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);  in sh_i2c_raw_read()
195 	readb(&dev->icdr); /* Dummy read */  in sh_i2c_raw_read()
207 	int num, denom, tmp;  in sh_i2c_init()  local
210 	if (!(gd->flags & GD_FLG_RELOC))  in sh_i2c_init()
215 	 * iccl = (p-clock / transfer-rate) * (L / (L + H))  in sh_i2c_init()
218 	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;  in sh_i2c_init()
220 	tmp = num * 10 / denom;  in sh_i2c_init()
222 		iccl = (u16)((num/denom) + 1);  in sh_i2c_init()
224 		iccl = (u16)(num/denom);  in sh_i2c_init()
227 	   icch = (p clock / transfer rate) * (H / (L + H)) */  in sh_i2c_init()
228 	num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;  in sh_i2c_init()
229 	tmp = num * 10 / denom;  in sh_i2c_init()
231 		icch = (u16)((num/denom) + 1);  in sh_i2c_init()
233 		icch = (u16)(num/denom);  in sh_i2c_init()
243 	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];  in sh_i2c_read()
248 			return -1;  in sh_i2c_read()
260 	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];  in sh_i2c_write()
266 			return -1;  in sh_i2c_write()
282 	struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];  in sh_i2c_set_bus_speed()