Lines Matching +full:num +full:- +full:transfer +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
126 /* Maximum transfer length for single DMA descriptor */
129 /* Maximum transfer length for all DMA descriptors */
134 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
135 * the top of maximum transfer time calculated from i2c bus speed to compensate
146 * data transfer
167 * total_tx_len: total tx length including tag bytes for current QUP transfer
168 * total_rx_len: total rx length including tag bytes for current QUP transfer
187 * tags: contains tx tag bytes for current QUP transfer
268 /* To check if the current transfer is using DMA */
284 /* function to write tags in tx fifo for i2c read transfer */
291 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt()
296 bus_err = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
297 qup_err = readl(qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
298 opflags = readl(qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
300 if (!qup->msg) { in qup_i2c_interrupt()
302 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
309 /* Clear the error bits in QUP_ERROR_FLAGS */ in qup_i2c_interrupt()
311 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
313 /* Clear the error bits in QUP_I2C_STATUS */ in qup_i2c_interrupt()
315 writel(bus_err, qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
319 * transfer. In Error case, sometimes, QUP generates more than one in qup_i2c_interrupt()
322 if (qup->use_dma && (qup->qup_err || qup->bus_err)) in qup_i2c_interrupt()
329 * flush operation needs to be scheduled in transfer function in qup_i2c_interrupt()
333 if (!qup->use_dma) in qup_i2c_interrupt()
334 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
339 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
342 blk->tx_fifo_free += qup->out_blk_sz; in qup_i2c_interrupt()
343 if (qup->msg->flags & I2C_M_RD) in qup_i2c_interrupt()
344 qup->write_rx_tags(qup); in qup_i2c_interrupt()
346 qup->write_tx_fifo(qup); in qup_i2c_interrupt()
351 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
353 if (!blk->is_rx_blk_mode) { in qup_i2c_interrupt()
354 blk->fifo_available += qup->in_fifo_sz; in qup_i2c_interrupt()
355 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
357 blk->fifo_available += qup->in_blk_sz; in qup_i2c_interrupt()
358 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
362 if (qup->msg->flags & I2C_M_RD) { in qup_i2c_interrupt()
363 if (!blk->rx_bytes_read) in qup_i2c_interrupt()
373 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) in qup_i2c_interrupt()
378 qup->qup_err = qup_err; in qup_i2c_interrupt()
379 qup->bus_err = bus_err; in qup_i2c_interrupt()
380 complete(&qup->xfer); in qup_i2c_interrupt()
395 state = readl(qup->base + QUP_STATE); in qup_i2c_poll_state_mask()
402 } while (retries--); in qup_i2c_poll_state_mask()
404 return -ETIMEDOUT; in qup_i2c_poll_state_mask()
414 u32 val = readl(qup->base + QUP_STATE); in qup_i2c_flush()
417 writel(val, qup->base + QUP_STATE); in qup_i2c_flush()
433 return -EIO; in qup_i2c_change_state()
435 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
438 return -EIO; in qup_i2c_change_state()
451 status = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_bus_active()
456 ret = -ETIMEDOUT; in qup_i2c_bus_active()
469 if (qup->cur_bw_clk_freq == clk_freq) in qup_i2c_vote_bw()
473 ret = icc_set_bw(qup->icc_path, 0, needed_peak_bw); in qup_i2c_vote_bw()
477 qup->cur_bw_clk_freq = clk_freq; in qup_i2c_vote_bw()
483 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1()
484 struct i2c_msg *msg = qup->msg; in qup_i2c_write_tx_fifo_v1()
490 if (qup->pos == 0) { in qup_i2c_write_tx_fifo_v1()
493 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
499 while (blk->tx_fifo_free && qup->pos < msg->len) { in qup_i2c_write_tx_fifo_v1()
500 if (qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
506 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; in qup_i2c_write_tx_fifo_v1()
508 val = qup_tag | msg->buf[qup->pos]; in qup_i2c_write_tx_fifo_v1()
511 if (idx & 1 || qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
512 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v1()
514 qup->pos++; in qup_i2c_write_tx_fifo_v1()
516 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
523 qup->blk.pos = 0; in qup_i2c_set_blk_data()
524 qup->blk.data_len = msg->len; in qup_i2c_set_blk_data()
525 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); in qup_i2c_set_blk_data()
532 if (qup->blk.data_len > qup->blk_xfer_limit) in qup_i2c_get_data_len()
533 data_len = qup->blk_xfer_limit; in qup_i2c_get_data_len()
535 data_len = qup->blk.data_len; in qup_i2c_get_data_len()
542 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); in qup_i2c_check_msg_len()
550 if (qup->is_smbus_read) { in qup_i2c_set_tags_smb()
557 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags_smb()
574 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); in qup_i2c_set_tags()
580 if (qup->blk.pos == 0) { in qup_i2c_set_tags()
584 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags()
590 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
595 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
596 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? in qup_i2c_set_tags()
619 complete(&qup->xfer); in qup_i2c_bam_cb()
629 ret = dma_map_sg(qup->dev, sg, 1, dir); in qup_sg_set_buf()
631 return -EINVAL; in qup_sg_set_buf()
638 if (qup->btx.dma) in qup_i2c_rel_dma()
639 dma_release_channel(qup->btx.dma); in qup_i2c_rel_dma()
640 if (qup->brx.dma) in qup_i2c_rel_dma()
641 dma_release_channel(qup->brx.dma); in qup_i2c_rel_dma()
642 qup->btx.dma = NULL; in qup_i2c_rel_dma()
643 qup->brx.dma = NULL; in qup_i2c_rel_dma()
650 if (!qup->btx.dma) { in qup_i2c_req_dma()
651 qup->btx.dma = dma_request_chan(qup->dev, "tx"); in qup_i2c_req_dma()
652 if (IS_ERR(qup->btx.dma)) { in qup_i2c_req_dma()
653 err = PTR_ERR(qup->btx.dma); in qup_i2c_req_dma()
654 qup->btx.dma = NULL; in qup_i2c_req_dma()
655 dev_err(qup->dev, "\n tx channel not available"); in qup_i2c_req_dma()
660 if (!qup->brx.dma) { in qup_i2c_req_dma()
661 qup->brx.dma = dma_request_chan(qup->dev, "rx"); in qup_i2c_req_dma()
662 if (IS_ERR(qup->brx.dma)) { in qup_i2c_req_dma()
663 dev_err(qup->dev, "\n rx channel not available"); in qup_i2c_req_dma()
664 err = PTR_ERR(qup->brx.dma); in qup_i2c_req_dma()
665 qup->brx.dma = NULL; in qup_i2c_req_dma()
680 qup->blk_xfer_limit = QUP_READ_LIMIT; in qup_i2c_bam_make_desc()
683 blocks = qup->blk.count; in qup_i2c_bam_make_desc()
684 rem = msg->len - (blocks - 1) * limit; in qup_i2c_bam_make_desc()
686 if (msg->flags & I2C_M_RD) { in qup_i2c_bam_make_desc()
687 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
688 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
689 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; in qup_i2c_bam_make_desc()
691 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
694 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
695 &qup->brx.tag.start[0], in qup_i2c_bam_make_desc()
701 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
702 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
709 qup->blk.pos = i; in qup_i2c_bam_make_desc()
711 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
712 &qup->start_tag.start[qup->tag_buf_pos], in qup_i2c_bam_make_desc()
717 qup->tag_buf_pos += len; in qup_i2c_bam_make_desc()
719 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
720 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
721 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; in qup_i2c_bam_make_desc()
723 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
725 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
732 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
733 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
738 qup->blk.pos = i; in qup_i2c_bam_make_desc()
741 qup->tag_buf_pos += tx_len; in qup_i2c_bam_make_desc()
753 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; in qup_i2c_bam_schedule_desc()
758 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; in qup_i2c_bam_schedule_desc()
762 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], in qup_i2c_bam_schedule_desc()
763 &qup->brx.tag.start[0], in qup_i2c_bam_schedule_desc()
769 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; in qup_i2c_bam_schedule_desc()
770 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], in qup_i2c_bam_schedule_desc()
775 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, in qup_i2c_bam_schedule_desc()
779 dev_err(qup->dev, "failed to get tx desc\n"); in qup_i2c_bam_schedule_desc()
780 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
785 txd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
786 txd->callback_param = qup; in qup_i2c_bam_schedule_desc()
791 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
795 dma_async_issue_pending(qup->btx.dma); in qup_i2c_bam_schedule_desc()
798 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, in qup_i2c_bam_schedule_desc()
802 dev_err(qup->dev, "failed to get rx desc\n"); in qup_i2c_bam_schedule_desc()
803 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
806 dmaengine_terminate_sync(qup->btx.dma); in qup_i2c_bam_schedule_desc()
810 rxd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
811 rxd->callback_param = qup; in qup_i2c_bam_schedule_desc()
814 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
818 dma_async_issue_pending(qup->brx.dma); in qup_i2c_bam_schedule_desc()
821 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) { in qup_i2c_bam_schedule_desc()
822 dev_err(qup->dev, "normal trans timed out\n"); in qup_i2c_bam_schedule_desc()
823 ret = -ETIMEDOUT; in qup_i2c_bam_schedule_desc()
826 if (ret || qup->bus_err || qup->qup_err) { in qup_i2c_bam_schedule_desc()
827 reinit_completion(&qup->xfer); in qup_i2c_bam_schedule_desc()
831 dev_err(qup->dev, "change to run state timed out"); in qup_i2c_bam_schedule_desc()
838 if (!wait_for_completion_timeout(&qup->xfer, HZ)) in qup_i2c_bam_schedule_desc()
839 dev_err(qup->dev, "flush timed out\n"); in qup_i2c_bam_schedule_desc()
841 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_bam_schedule_desc()
845 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
848 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, in qup_i2c_bam_schedule_desc()
856 qup->btx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
857 qup->brx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
858 qup->tag_buf_pos = 0; in qup_i2c_bam_clear_tag_buffers()
862 int num) in qup_i2c_bam_xfer() argument
868 ret = qup_i2c_vote_bw(qup, qup->src_clk_freq); in qup_i2c_bam_xfer()
872 enable_irq(qup->irq); in qup_i2c_bam_xfer()
878 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_bam_xfer()
879 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_bam_xfer()
882 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); in qup_i2c_bam_xfer()
885 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); in qup_i2c_bam_xfer()
892 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()
895 for (idx = 0; idx < num; idx++) { in qup_i2c_bam_xfer()
896 qup->msg = msg + idx; in qup_i2c_bam_xfer()
897 qup->is_last = idx == (num - 1); in qup_i2c_bam_xfer()
899 ret = qup_i2c_bam_make_desc(qup, qup->msg); in qup_i2c_bam_xfer()
904 * Make DMA descriptor and schedule the BAM transfer if its in qup_i2c_bam_xfer()
910 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
911 qup->brx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
912 qup->is_last) { in qup_i2c_bam_xfer()
922 disable_irq(qup->irq); in qup_i2c_bam_xfer()
924 qup->msg = NULL; in qup_i2c_bam_xfer()
934 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); in qup_i2c_wait_for_complete()
936 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_wait_for_complete()
937 ret = -ETIMEDOUT; in qup_i2c_wait_for_complete()
940 if (qup->bus_err || qup->qup_err) in qup_i2c_wait_for_complete()
941 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_wait_for_complete()
948 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1()
949 struct i2c_msg *msg = qup->msg; in qup_i2c_read_rx_fifo_v1()
953 while (blk->fifo_available && qup->pos < msg->len) { in qup_i2c_read_rx_fifo_v1()
956 val = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_read_rx_fifo_v1()
957 msg->buf[qup->pos++] = val & 0xFF; in qup_i2c_read_rx_fifo_v1()
959 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; in qup_i2c_read_rx_fifo_v1()
962 blk->fifo_available--; in qup_i2c_read_rx_fifo_v1()
965 if (qup->pos == msg->len) in qup_i2c_read_rx_fifo_v1()
966 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v1()
971 struct i2c_msg *msg = qup->msg; in qup_i2c_write_rx_tags_v1()
977 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; in qup_i2c_write_rx_tags_v1()
980 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v1()
985 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1()
989 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz; in qup_i2c_conf_v1()
990 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz; in qup_i2c_conf_v1()
992 if (blk->is_tx_blk_mode) { in qup_i2c_conf_v1()
994 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
995 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
997 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
998 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
1001 if (blk->total_rx_len) { in qup_i2c_conf_v1()
1002 if (blk->is_rx_blk_mode) { in qup_i2c_conf_v1()
1004 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
1005 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
1007 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
1008 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
1014 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_v1()
1015 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_v1()
1020 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v1()
1021 blk->fifo_available = 0; in qup_i2c_clear_blk_v1()
1022 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v1()
1027 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1()
1036 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()
1042 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v1()
1043 enable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1044 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v1()
1045 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v1()
1057 ret = qup_i2c_wait_for_complete(qup, qup->msg); in qup_i2c_conf_xfer_v1()
1064 disable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1070 struct i2c_msg *msg = qup->msg; in qup_i2c_write_one()
1071 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one()
1073 qup->pos = 0; in qup_i2c_write_one()
1074 blk->total_tx_len = msg->len + 1; in qup_i2c_write_one()
1075 blk->total_rx_len = 0; in qup_i2c_write_one()
1082 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one()
1084 qup->pos = 0; in qup_i2c_read_one()
1085 blk->total_tx_len = 2; in qup_i2c_read_one()
1086 blk->total_rx_len = qup->msg->len; in qup_i2c_read_one()
1093 int num) in qup_i2c_xfer() argument
1098 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer()
1102 qup->bus_err = 0; in qup_i2c_xfer()
1103 qup->qup_err = 0; in qup_i2c_xfer()
1105 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer()
1111 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); in qup_i2c_xfer()
1113 for (idx = 0; idx < num; idx++) { in qup_i2c_xfer()
1115 ret = -EIO; in qup_i2c_xfer()
1120 ret = -EINVAL; in qup_i2c_xfer()
1124 qup->msg = &msgs[idx]; in qup_i2c_xfer()
1139 ret = num; in qup_i2c_xfer()
1142 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer()
1143 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer()
1150 * before each i2c sub transfer.
1154 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2()
1157 if (blk->is_tx_blk_mode) in qup_i2c_conf_count_v2()
1158 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1159 qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_count_v2()
1161 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1162 qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_count_v2()
1164 if (blk->total_rx_len) { in qup_i2c_conf_count_v2()
1165 if (blk->is_rx_blk_mode) in qup_i2c_conf_count_v2()
1166 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1167 qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_count_v2()
1169 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1170 qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_count_v2()
1175 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_count_v2()
1179 * Configure registers related with transfer mode (FIFO/Block)
1180 * before starting of i2c transfer. It will be called only once in
1185 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2()
1188 if (blk->is_tx_blk_mode) { in qup_i2c_conf_mode_v2()
1190 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_mode_v2()
1192 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_mode_v2()
1195 if (blk->is_rx_blk_mode) { in qup_i2c_conf_mode_v2()
1197 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_mode_v2()
1199 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_mode_v2()
1202 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_mode_v2()
1205 /* Clear required variables before starting of any QUP v2 sub transfer. */
1208 blk->send_last_word = false; in qup_i2c_clear_blk_v2()
1209 blk->tx_tags_sent = false; in qup_i2c_clear_blk_v2()
1210 blk->tx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1211 blk->tx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1212 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v2()
1214 blk->rx_tags_fetched = false; in qup_i2c_clear_blk_v2()
1215 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v2()
1216 blk->rx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1217 blk->rx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1218 blk->fifo_available = 0; in qup_i2c_clear_blk_v2()
1221 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1224 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data()
1227 for (j = blk->rx_fifo_data_pos; in qup_i2c_recv_data()
1228 blk->cur_blk_len && blk->fifo_available; in qup_i2c_recv_data()
1229 blk->cur_blk_len--, blk->fifo_available--) { in qup_i2c_recv_data()
1231 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_data()
1233 *(blk->cur_data++) = blk->rx_fifo_data; in qup_i2c_recv_data()
1234 blk->rx_fifo_data >>= 8; in qup_i2c_recv_data()
1242 blk->rx_fifo_data_pos = j; in qup_i2c_recv_data()
1245 /* Receive tags for read message in QUP v2 i2c transfer. */
1248 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_tags()
1250 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_tags()
1251 blk->rx_fifo_data >>= blk->rx_tag_len * 8; in qup_i2c_recv_tags()
1252 blk->rx_fifo_data_pos = blk->rx_tag_len; in qup_i2c_recv_tags()
1253 blk->fifo_available -= blk->rx_tag_len; in qup_i2c_recv_tags()
1266 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v2()
1268 if (!blk->rx_tags_fetched) { in qup_i2c_read_rx_fifo_v2()
1270 blk->rx_tags_fetched = true; in qup_i2c_read_rx_fifo_v2()
1274 if (!blk->cur_blk_len) in qup_i2c_read_rx_fifo_v2()
1275 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v2()
1279 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1286 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_blk_data()
1289 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; in qup_i2c_write_blk_data()
1290 (*len)--, blk->tx_fifo_free--) { in qup_i2c_write_blk_data()
1291 blk->tx_fifo_data |= *(*data)++ << (j * 8); in qup_i2c_write_blk_data()
1293 writel(blk->tx_fifo_data, in qup_i2c_write_blk_data()
1294 qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_blk_data()
1295 blk->tx_fifo_data = 0x0; in qup_i2c_write_blk_data()
1302 blk->tx_fifo_data_pos = j; in qup_i2c_write_blk_data()
1305 /* Transfer tags for read message in QUP v2 i2c transfer. */
1308 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_rx_tags_v2()
1310 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); in qup_i2c_write_rx_tags_v2()
1311 if (blk->tx_fifo_data_pos) in qup_i2c_write_rx_tags_v2()
1312 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v2()
1339 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v2()
1341 if (!blk->tx_tags_sent) { in qup_i2c_write_tx_fifo_v2()
1342 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, in qup_i2c_write_tx_fifo_v2()
1343 &blk->tx_tag_len); in qup_i2c_write_tx_fifo_v2()
1344 blk->tx_tags_sent = true; in qup_i2c_write_tx_fifo_v2()
1347 if (blk->send_last_word) in qup_i2c_write_tx_fifo_v2()
1350 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); in qup_i2c_write_tx_fifo_v2()
1351 if (!blk->cur_blk_len) { in qup_i2c_write_tx_fifo_v2()
1352 if (!blk->tx_fifo_data_pos) in qup_i2c_write_tx_fifo_v2()
1355 if (blk->tx_fifo_free) in qup_i2c_write_tx_fifo_v2()
1358 blk->send_last_word = true; in qup_i2c_write_tx_fifo_v2()
1364 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v2()
1368 * Main transfer function which read or write i2c data.
1376 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v2()
1377 struct i2c_msg *msg = qup->msg; in qup_i2c_conf_xfer_v2()
1386 if (qup->is_smbus_read) { in qup_i2c_conf_xfer_v2()
1392 blk->cur_data += 1; in qup_i2c_conf_xfer_v2()
1399 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; in qup_i2c_conf_xfer_v2()
1404 /* If it is first sub transfer, then configure i2c bus clocks */ in qup_i2c_conf_xfer_v2()
1410 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()
1417 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v2()
1418 enable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1423 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v2()
1424 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v2()
1448 disable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1453 * Transfer one read/write message in i2c transfer. It splits the message into
1461 struct i2c_msg *msg = qup->msg; in qup_i2c_xfer_v2_msg()
1462 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_xfer_v2_msg()
1463 u8 *msg_buf = msg->buf; in qup_i2c_xfer_v2_msg()
1465 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; in qup_i2c_xfer_v2_msg()
1468 for (i = 0; i < blk->count; i++) { in qup_i2c_xfer_v2_msg()
1470 blk->pos = i; in qup_i2c_xfer_v2_msg()
1471 blk->cur_tx_tags = blk->tags; in qup_i2c_xfer_v2_msg()
1472 blk->cur_blk_len = data_len; in qup_i2c_xfer_v2_msg()
1473 blk->tx_tag_len = in qup_i2c_xfer_v2_msg()
1474 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); in qup_i2c_xfer_v2_msg()
1476 blk->cur_data = msg_buf; in qup_i2c_xfer_v2_msg()
1479 blk->total_tx_len = blk->tx_tag_len; in qup_i2c_xfer_v2_msg()
1480 blk->rx_tag_len = 2; in qup_i2c_xfer_v2_msg()
1481 blk->total_rx_len = blk->rx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1483 blk->total_tx_len = blk->tx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1484 blk->total_rx_len = 0; in qup_i2c_xfer_v2_msg()
1488 !qup->is_last || i < blk->count - 1); in qup_i2c_xfer_v2_msg()
1493 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && in qup_i2c_xfer_v2_msg()
1494 !qup->is_smbus_read) { in qup_i2c_xfer_v2_msg()
1495 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) in qup_i2c_xfer_v2_msg()
1496 return -EPROTO; in qup_i2c_xfer_v2_msg()
1498 msg->len = msg->buf[0]; in qup_i2c_xfer_v2_msg()
1499 qup->is_smbus_read = true; in qup_i2c_xfer_v2_msg()
1501 qup->is_smbus_read = false; in qup_i2c_xfer_v2_msg()
1505 msg->len += 1; in qup_i2c_xfer_v2_msg()
1509 blk->data_len -= qup->blk_xfer_limit; in qup_i2c_xfer_v2_msg()
1522 * This function determines the mode which will be used for this transfer. An
1523 * i2c transfer contains multiple message. Following are the rules to determine
1525 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1526 * 2. If complete transfer length is greater than fifo size then use the DMA
1533 struct i2c_msg msgs[], int num) in qup_i2c_determine_mode_v2() argument
1540 for (idx = 0; idx < num; idx++) { in qup_i2c_determine_mode_v2()
1554 if (!no_dma && qup->is_dma && in qup_i2c_determine_mode_v2()
1555 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { in qup_i2c_determine_mode_v2()
1556 qup->use_dma = true; in qup_i2c_determine_mode_v2()
1558 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - in qup_i2c_determine_mode_v2()
1560 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - in qup_i2c_determine_mode_v2()
1569 int num) in qup_i2c_xfer_v2() argument
1574 qup->bus_err = 0; in qup_i2c_xfer_v2()
1575 qup->qup_err = 0; in qup_i2c_xfer_v2()
1577 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer_v2()
1581 ret = qup_i2c_determine_mode_v2(qup, msgs, num); in qup_i2c_xfer_v2()
1585 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer_v2()
1591 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); in qup_i2c_xfer_v2()
1592 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); in qup_i2c_xfer_v2()
1595 ret = -EIO; in qup_i2c_xfer_v2()
1599 if (qup->use_dma) { in qup_i2c_xfer_v2()
1600 reinit_completion(&qup->xfer); in qup_i2c_xfer_v2()
1601 ret = qup_i2c_bam_xfer(adap, &msgs[0], num); in qup_i2c_xfer_v2()
1602 qup->use_dma = false; in qup_i2c_xfer_v2()
1606 for (idx = 0; idx < num; idx++) { in qup_i2c_xfer_v2()
1607 qup->msg = &msgs[idx]; in qup_i2c_xfer_v2()
1608 qup->is_last = idx == (num - 1); in qup_i2c_xfer_v2()
1615 qup->msg = NULL; in qup_i2c_xfer_v2()
1625 ret = num; in qup_i2c_xfer_v2()
1627 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer_v2()
1628 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer_v2()
1664 clk_prepare_enable(qup->clk); in qup_i2c_enable_clocks()
1665 clk_prepare_enable(qup->pclk); in qup_i2c_enable_clocks()
1673 clk_disable_unprepare(qup->clk); in qup_i2c_disable_clocks()
1674 config = readl(qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1676 writel(config, qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1678 clk_disable_unprepare(qup->pclk); in qup_i2c_disable_clocks()
1699 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); in qup_i2c_probe()
1701 return -ENOMEM; in qup_i2c_probe()
1703 qup->dev = &pdev->dev; in qup_i2c_probe()
1704 init_completion(&qup->xfer); in qup_i2c_probe()
1708 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); in qup_i2c_probe()
1711 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); in qup_i2c_probe()
1713 dev_notice(qup->dev, "using default clock-frequency %d", in qup_i2c_probe()
1718 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { in qup_i2c_probe()
1719 qup->adap.algo = &qup_i2c_algo; in qup_i2c_probe()
1720 qup->adap.quirks = &qup_i2c_quirks; in qup_i2c_probe()
1723 qup->adap.algo = &qup_i2c_algo_v2; in qup_i2c_probe()
1724 qup->adap.quirks = &qup_i2c_quirks_v2; in qup_i2c_probe()
1726 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) in qup_i2c_probe()
1731 if (ret == -EPROBE_DEFER) in qup_i2c_probe()
1736 qup->max_xfer_sg_len = (MX_BLOCKS << 1); in qup_i2c_probe()
1738 qup->btx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1739 blocks, sizeof(*qup->btx.sg), in qup_i2c_probe()
1741 if (!qup->btx.sg) { in qup_i2c_probe()
1742 ret = -ENOMEM; in qup_i2c_probe()
1745 sg_init_table(qup->btx.sg, blocks); in qup_i2c_probe()
1747 qup->brx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1748 blocks, sizeof(*qup->brx.sg), in qup_i2c_probe()
1750 if (!qup->brx.sg) { in qup_i2c_probe()
1751 ret = -ENOMEM; in qup_i2c_probe()
1754 sg_init_table(qup->brx.sg, blocks); in qup_i2c_probe()
1759 qup->start_tag.start = devm_kzalloc(&pdev->dev, in qup_i2c_probe()
1761 if (!qup->start_tag.start) { in qup_i2c_probe()
1762 ret = -ENOMEM; in qup_i2c_probe()
1766 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1767 if (!qup->brx.tag.start) { in qup_i2c_probe()
1768 ret = -ENOMEM; in qup_i2c_probe()
1772 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1773 if (!qup->btx.tag.start) { in qup_i2c_probe()
1774 ret = -ENOMEM; in qup_i2c_probe()
1777 qup->is_dma = true; in qup_i2c_probe()
1779 qup->icc_path = devm_of_icc_get(&pdev->dev, NULL); in qup_i2c_probe()
1780 if (IS_ERR(qup->icc_path)) in qup_i2c_probe()
1781 return dev_err_probe(&pdev->dev, PTR_ERR(qup->icc_path), in qup_i2c_probe()
1788 dev_err(qup->dev, "clock frequency not supported %d\n", in qup_i2c_probe()
1790 ret = -EINVAL; in qup_i2c_probe()
1794 qup->base = devm_platform_ioremap_resource(pdev, 0); in qup_i2c_probe()
1795 if (IS_ERR(qup->base)) { in qup_i2c_probe()
1796 ret = PTR_ERR(qup->base); in qup_i2c_probe()
1800 qup->irq = platform_get_irq(pdev, 0); in qup_i2c_probe()
1801 if (qup->irq < 0) { in qup_i2c_probe()
1802 ret = qup->irq; in qup_i2c_probe()
1806 if (has_acpi_companion(qup->dev)) { in qup_i2c_probe()
1807 ret = device_property_read_u32(qup->dev, in qup_i2c_probe()
1808 "src-clock-hz", &src_clk_freq); in qup_i2c_probe()
1810 dev_notice(qup->dev, "using default src-clock-hz %d", in qup_i2c_probe()
1813 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); in qup_i2c_probe()
1815 qup->clk = devm_clk_get(qup->dev, "core"); in qup_i2c_probe()
1816 if (IS_ERR(qup->clk)) { in qup_i2c_probe()
1817 dev_err(qup->dev, "Could not get core clock\n"); in qup_i2c_probe()
1818 ret = PTR_ERR(qup->clk); in qup_i2c_probe()
1822 qup->pclk = devm_clk_get(qup->dev, "iface"); in qup_i2c_probe()
1823 if (IS_ERR(qup->pclk)) { in qup_i2c_probe()
1824 dev_err(qup->dev, "Could not get iface clock\n"); in qup_i2c_probe()
1825 ret = PTR_ERR(qup->pclk); in qup_i2c_probe()
1829 src_clk_freq = clk_get_rate(qup->clk); in qup_i2c_probe()
1831 qup->src_clk_freq = src_clk_freq; in qup_i2c_probe()
1837 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_probe()
1842 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, in qup_i2c_probe()
1846 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); in qup_i2c_probe()
1850 hw_ver = readl(qup->base + QUP_HW_VERSION); in qup_i2c_probe()
1851 dev_dbg(qup->dev, "Revision %x\n", hw_ver); in qup_i2c_probe()
1853 io_mode = readl(qup->base + QUP_IO_MODE); in qup_i2c_probe()
1861 ret = -EIO; in qup_i2c_probe()
1864 qup->out_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1868 ret = -EIO; in qup_i2c_probe()
1871 qup->in_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1875 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a in qup_i2c_probe()
1876 * single transfer but the block size is in bytes so divide the in qup_i2c_probe()
1879 qup->in_blk_sz /= 2; in qup_i2c_probe()
1880 qup->out_blk_sz /= 2; in qup_i2c_probe()
1881 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; in qup_i2c_probe()
1882 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; in qup_i2c_probe()
1883 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; in qup_i2c_probe()
1885 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; in qup_i2c_probe()
1886 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; in qup_i2c_probe()
1887 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; in qup_i2c_probe()
1891 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); in qup_i2c_probe()
1894 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); in qup_i2c_probe()
1898 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; in qup_i2c_probe()
1899 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1902 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; in qup_i2c_probe()
1903 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1908 * Each byte takes 9 clock cycles (8 bits + 1 ack). in qup_i2c_probe()
1911 qup->one_byte_t = one_bit_t * 9; in qup_i2c_probe()
1912 qup->xfer_timeout = TOUT_MIN * HZ + in qup_i2c_probe()
1913 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); in qup_i2c_probe()
1915 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", in qup_i2c_probe()
1916 qup->in_blk_sz, qup->in_fifo_sz, in qup_i2c_probe()
1917 qup->out_blk_sz, qup->out_fifo_sz); in qup_i2c_probe()
1919 i2c_set_adapdata(&qup->adap, qup); in qup_i2c_probe()
1920 qup->adap.dev.parent = qup->dev; in qup_i2c_probe()
1921 qup->adap.dev.of_node = pdev->dev.of_node; in qup_i2c_probe()
1922 qup->is_last = true; in qup_i2c_probe()
1924 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); in qup_i2c_probe()
1926 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); in qup_i2c_probe()
1927 pm_runtime_use_autosuspend(qup->dev); in qup_i2c_probe()
1928 pm_runtime_set_active(qup->dev); in qup_i2c_probe()
1929 pm_runtime_enable(qup->dev); in qup_i2c_probe()
1931 ret = i2c_add_adapter(&qup->adap); in qup_i2c_probe()
1938 pm_runtime_disable(qup->dev); in qup_i2c_probe()
1939 pm_runtime_set_suspended(qup->dev); in qup_i2c_probe()
1943 if (qup->btx.dma) in qup_i2c_probe()
1944 dma_release_channel(qup->btx.dma); in qup_i2c_probe()
1945 if (qup->brx.dma) in qup_i2c_probe()
1946 dma_release_channel(qup->brx.dma); in qup_i2c_probe()
1954 if (qup->is_dma) { in qup_i2c_remove()
1955 dma_release_channel(qup->btx.dma); in qup_i2c_remove()
1956 dma_release_channel(qup->brx.dma); in qup_i2c_remove()
1959 disable_irq(qup->irq); in qup_i2c_remove()
1961 i2c_del_adapter(&qup->adap); in qup_i2c_remove()
1962 pm_runtime_disable(qup->dev); in qup_i2c_remove()
1963 pm_runtime_set_suspended(qup->dev); in qup_i2c_remove()
2006 { .compatible = "qcom,i2c-qup-v1.1.1" },
2007 { .compatible = "qcom,i2c-qup-v2.1.1" },
2008 { .compatible = "qcom,i2c-qup-v2.2.1" },