| /openbmc/u-boot/board/sbc8548/ |
| H A D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
31 * TLB 0: 64M Non-cacheable, guarded
33 * 0xff800000 8M boot FLASH
35 * 0xfc000000 64M user flash
44 * TLB 1: 1G Non-cacheable, guarded
53 * TLB 2: 64M Non-cacheable, guarded
64 * TLB 3: 64M Cacheable, non-guarded
72 * TLB 4: 64M Cacheable, non-guarded
82 * TLB 5: 16M Cacheable, non-guarded
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| /openbmc/u-boot/drivers/mtd/ |
| H A D | Kconfig | 11 flash, RAM and similar chips, often used for solid state file
15 bool "Enable parallel NOR flash support"
17 Enable support for parallel NOR flash.
26 bool "Enable CFI Flash driver"
28 The Common Flash Interface specification was developed by Intel,
29 AMD and other flash manufactures. It provides a universal method
30 for probing the capabilities of flash devices. If you wish to
31 support any device that is CFI-compliant, you need to enable this
36 bool "Enable Driver Model for CFI Flash driver"
39 The Common Flash Interface specification was developed by Intel,
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| /openbmc/u-boot/doc/ |
| H A D | README.ti-secure | 22 Booting of U-Boot SPL
25 When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process
36 ${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
38 This is called as part of the SPL/u-boot build process. As the secure
49 create-boot-image.sh \
55 SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
56 X-LOADER - Generates an image for non-XIP flash
57 MLO - Generates an image for SD/MMC/eMMC media
58 2ND - Generates an image for USB, UART and Ethernet
59 XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
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| H A D | README.update | 5 --------
8 server in NOR Flash. In more detail: a TFTP transfer of a file given in
11 updates. Each update in the update file has an address in NOR Flash where it
12 should be placed, updates are also protected with a SHA-1 checksum. If the
14 verification is positive, the update is stored in Flash.
16 The auto-update feature is enabled by the CONFIG_UPDATE_TFTP macro:
21 Note that when enabling auto-update, Flash support must be turned on. Also,
27 The auto-update feature uses the following configuration knobs:
29 - CONFIG_UPDATE_LOAD_ADDR
36 - CONFIG_UPDATE_TFTP_CNT_MAX
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| /openbmc/u-boot/include/configs/ |
| H A D | xpedite537x.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
81 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
82 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
83 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
84 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
85 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
86 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
87 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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| H A D | xpedite517x.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
28 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
68 * Base addresses -- Note these are effective addresses where the
90 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
91 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
92 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
93 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
94 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
95 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
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| H A D | xpedite550x.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
85 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
86 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
87 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
88 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
89 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
90 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
91 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
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| H A D | xpedite520x.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2004-2008 Freescale Semiconductor, Inc.
23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
68 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
69 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
70 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
71 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
72 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
73 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
74 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
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| H A D | MPC8548CDS.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
89 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
90 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
91 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
93 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
94 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
95 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
102 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
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| H A D | P1023RDB.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Authors: Roy Zang <tie-fei.zang@freescale.com>
28 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
71 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
72 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
73 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
75 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
78 * Localbus non-cacheable
80 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
81 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
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| H A D | MPC8544DS.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
76 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
78 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
80 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
81 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
88 * Localbus non-cacheable
90 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
91 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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| H A D | edb93xx.h | 2 * U-Boot - Configuration file for Cirrus Logic EDB93xx boards
34 #define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds"
71 /* High-level configuration options */
103 * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
104 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
105 * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
108 * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
117 * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
118 * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
119 * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
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| H A D | README.P1010RDB-PB | 3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
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| /openbmc/u-boot/drivers/fastboot/ |
| H A D | Kconfig | 66 bool "Enable FASTBOOT FLASH command"
71 The fastboot protocol includes a "flash" command for writing
72 the downloaded image to a non-volatile storage device. Define
73 this to enable the "fastboot flash" command.
76 prompt "Flash provider for FASTBOOT"
90 int "Define FASTBOOT MMC FLASH default device"
92 default 0 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
93 default 1 if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
95 The fastboot "flash" command requires additional information
96 regarding the non-volatile storage device. Define this to
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| /openbmc/u-boot/arch/x86/include/asm/ |
| H A D | mrccache.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
33 * mrccache_find_current() - find the latest MRC cache record
38 * @entry: Position and size of MRC cache in SPI flash
44 * mrccache_update() - update the MRC cache with a new record
49 * @sf: SPI flash to write to
50 * @entry: Position and size of MRC cache in SPI flash
52 * @return 0 if updated, -EEXIST if the record is the same as the latest
53 * record, -EINVAL if the record is not valid, other error if SPI write failed
59 * mrccache_reserve() - reserve MRC data on the stack
61 * This copies MRC data pointed by gd->arch.mrc_output to a new place on the
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-mtd | 4 Contact: linux-mtd@lists.infradead.org
12 Contact: linux-mtd@lists.infradead.org
16 physical/simulated flash devices, partitions on a flash
17 device, or concatenated flash devices.
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
39 Contact: linux-mtd@lists.infradead.org
42 to the read-only variant of the MTD device (in
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| H A D | sysfs-bus-spi-devices-spi-nor | 1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
6 flash device.
8 The attribute is not present if the flash doesn't support
10 non-JEDEC compliant flashes.
12 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
15 Contact: linux-mtd@lists.infradead.org
16 Description: (RO) Manufacturer of the SPI NOR flash.
18 The attribute is not present if the flash device isn't
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | nand_spl_loaders.c | 8 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; in nand_spl_load_image()
26 dst = (void *)((int)dst - page_offset); in nand_spl_load_image()
46 * Temporary storage for non NAND page aligned and non NAND page sized
47 * reads. Note: This does not support runtime detected FLASH yet, but
54 * nand_spl_read_block - Read data from physical eraseblock into a buffer
69 * To support runtime detected flash this needs to be extended by
70 * information about the actual flash geometry, but thats beyond the
81 /* Offset to the start of a flash page */ in nand_spl_read_block()
86 * Non page aligned reads go to the scratch buffer. in nand_spl_read_block()
91 read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset); in nand_spl_read_block()
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| /openbmc/linux/drivers/mtd/chips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
23 compatible with the Common Flash Interface, but will use the common
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| /openbmc/linux/drivers/mtd/devices/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "Self-contained MTD device drivers"
12 These devices come in memory configurations from 32M - 1G. If you
41 tristate "DEC MS02-NV NVRAM module support"
44 This is an MTD driver for the DEC's MS02-NV (54-20948-01) battery
45 backed-up NVRAM module. The module was originally meant as an NFS
52 The module will be called ms02-nv.
59 Sometimes DataFlash chips are packaged inside MMC-format
66 This adds an extra check when data is written to the flash.
77 one-time-programmable (OTP) data. The first half may be written
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| /openbmc/linux/Documentation/leds/ |
| H A D | leds-class-flash.rst | 2 Flash LED handling under Linux
5 Some LED devices provide two modes - torch and flash. In the LED subsystem
6 those modes are supported by LED class (see Documentation/leds/leds-class.rst)
7 and LED Flash class respectively. The torch mode related features are enabled
8 by default and the flash ones only if a driver declares it by setting
11 In order to enable the support for flash LEDs CONFIG_LEDS_CLASS_FLASH symbol
12 must be defined in the kernel config. A LED Flash class driver must be
15 Following sysfs attributes are exposed for controlling flash LED devices:
16 (see Documentation/ABI/testing/sysfs-class-led-flash)
18 - flash_brightness
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| /openbmc/u-boot/board/freescale/mpc8568mds/ |
| H A D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
29 * TLBe 0: 16M Non-cacheable, guarded
30 * 0xff000000 16M FLASH (upper half)
38 * TLBe 1: 16M Non-cacheable, guarded
39 * 0xfe000000 16M FLASH (lower half)
46 * TLBe 2: 1G Non-cacheable, guarded
55 * TLBe 3: 64M Non-cacheable, guarded
65 * TLBe 4: 64M Cacheable, non-guarded
73 * TLBe 5: 256K Non-cacheable, guarded
|
| /openbmc/qemu/hw/i386/ |
| H A D | pc_sysfw.c | 4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2011-2012 Intel Corporation
28 #include "sysemu/block-backend.h"
29 #include "qemu/error-report.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/block/flash.h"
55 memory_region_init_ram_guest_memfd(isa_bios, NULL, "isa-bios", in pc_isa_bios_init()
58 memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size, in pc_isa_bios_init()
62 0x100000 - isa_bios_size, in pc_isa_bios_init()
66 /* copy ISA rom image from top of flash memory */ in pc_isa_bios_init()
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| /openbmc/linux/drivers/mtd/spi-nor/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 Many flash memories support erasing small (4096 B) sectors. Depending
20 Changing a small part of the flash's contents is usually faster with
35 flashes at boot-up.
37 Depending on the flash chip this either clears the block protection
41 of your SPI flash. This is only to keep backwards compatibility.
47 power-up or a reset the flash is software write protected by
52 which have non-volatile write protection bits.
55 the flash either the block protection bits are cleared or a
64 SPI flashes will not be changed. If your flash is software write
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