1*f1056910SThomas ChouCFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...) 2*f1056910SThomas Chou 3*f1056910SThomas ChouFlash chips (Memory Technology Devices) are often used for solid state 4*f1056910SThomas Choufile systems on embedded devices. 5*f1056910SThomas Chou 6*f1056910SThomas Chou - compatible : should contain the specific model of mtd chip(s) 7*f1056910SThomas Chou used, if known, followed by either "cfi-flash", "jedec-flash", 8*f1056910SThomas Chou "mtd-ram" or "mtd-rom". 9*f1056910SThomas Chou - reg : Address range(s) of the mtd chip(s) 10*f1056910SThomas Chou It's possible to (optionally) define multiple "reg" tuples so that 11*f1056910SThomas Chou non-identical chips can be described in one node. 12*f1056910SThomas Chou - bank-width : Width (in bytes) of the bank. Equal to the 13*f1056910SThomas Chou device width times the number of interleaved chips. 14*f1056910SThomas Chou - device-width : (optional) Width of a single mtd chip. If 15*f1056910SThomas Chou omitted, assumed to be equal to 'bank-width'. 16*f1056910SThomas Chou - #address-cells, #size-cells : Must be present if the device has 17*f1056910SThomas Chou sub-nodes representing partitions (see below). In this case 18*f1056910SThomas Chou both #address-cells and #size-cells must be equal to 1. 19*f1056910SThomas Chou - no-unaligned-direct-access: boolean to disable the default direct 20*f1056910SThomas Chou mapping of the flash. 21*f1056910SThomas Chou On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause 22*f1056910SThomas Chou problems with JFFS2 usage, as the local bus (LPB) doesn't support 23*f1056910SThomas Chou unaligned accesses as implemented in the JFFS2 code via memcpy(). 24*f1056910SThomas Chou By defining "no-unaligned-direct-access", the flash will not be 25*f1056910SThomas Chou exposed directly to the MTD users (e.g. JFFS2) any more. 26*f1056910SThomas Chou - linux,mtd-name: allow to specify the mtd name for retro capability with 27*f1056910SThomas Chou physmap-flash drivers as boot loader pass the mtd partition via the old 28*f1056910SThomas Chou device name physmap-flash. 29*f1056910SThomas Chou - use-advanced-sector-protection: boolean to enable support for the 30*f1056910SThomas Chou advanced sector protection (Spansion: PPB - Persistent Protection 31*f1056910SThomas Chou Bits) locking. 32*f1056910SThomas Chou 33*f1056910SThomas ChouFor JEDEC compatible devices, the following additional properties 34*f1056910SThomas Chouare defined: 35*f1056910SThomas Chou 36*f1056910SThomas Chou - vendor-id : Contains the flash chip's vendor id (1 byte). 37*f1056910SThomas Chou - device-id : Contains the flash chip's device id (1 byte). 38*f1056910SThomas Chou 39*f1056910SThomas ChouFor ROM compatible devices (and ROM fallback from cfi-flash), the following 40*f1056910SThomas Chouadditional (optional) property is defined: 41*f1056910SThomas Chou 42*f1056910SThomas Chou - erase-size : The chip's physical erase block size in bytes. 43*f1056910SThomas Chou 44*f1056910SThomas ChouThe device tree may optionally contain sub-nodes describing partitions of the 45*f1056910SThomas Chouaddress space. See partition.txt for more detail. 46*f1056910SThomas Chou 47*f1056910SThomas ChouExample: 48*f1056910SThomas Chou 49*f1056910SThomas Chou flash@ff000000 { 50*f1056910SThomas Chou compatible = "amd,am29lv128ml", "cfi-flash"; 51*f1056910SThomas Chou reg = <ff000000 01000000>; 52*f1056910SThomas Chou bank-width = <4>; 53*f1056910SThomas Chou device-width = <1>; 54*f1056910SThomas Chou #address-cells = <1>; 55*f1056910SThomas Chou #size-cells = <1>; 56*f1056910SThomas Chou fs@0 { 57*f1056910SThomas Chou label = "fs"; 58*f1056910SThomas Chou reg = <0 f80000>; 59*f1056910SThomas Chou }; 60*f1056910SThomas Chou firmware@f80000 { 61*f1056910SThomas Chou label ="firmware"; 62*f1056910SThomas Chou reg = <f80000 80000>; 63*f1056910SThomas Chou read-only; 64*f1056910SThomas Chou }; 65*f1056910SThomas Chou }; 66*f1056910SThomas Chou 67*f1056910SThomas ChouHere an example with multiple "reg" tuples: 68*f1056910SThomas Chou 69*f1056910SThomas Chou flash@f0000000,0 { 70*f1056910SThomas Chou #address-cells = <1>; 71*f1056910SThomas Chou #size-cells = <1>; 72*f1056910SThomas Chou compatible = "intel,pc48f4400p0vb", "cfi-flash"; 73*f1056910SThomas Chou reg = <0 0x00000000 0x02000000 74*f1056910SThomas Chou 0 0x02000000 0x02000000>; 75*f1056910SThomas Chou bank-width = <2>; 76*f1056910SThomas Chou partition@0 { 77*f1056910SThomas Chou label = "test-part1"; 78*f1056910SThomas Chou reg = <0 0x04000000>; 79*f1056910SThomas Chou }; 80*f1056910SThomas Chou }; 81*f1056910SThomas Chou 82*f1056910SThomas ChouAn example using SRAM: 83*f1056910SThomas Chou 84*f1056910SThomas Chou sram@2,0 { 85*f1056910SThomas Chou compatible = "samsung,k6f1616u6a", "mtd-ram"; 86*f1056910SThomas Chou reg = <2 0 0x00200000>; 87*f1056910SThomas Chou bank-width = <2>; 88*f1056910SThomas Chou }; 89