Lines Matching +full:non +full:- +full:flash
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
89 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
90 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
91 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
93 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
94 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
95 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
102 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
103 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
104 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
106 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
107 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
108 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
117 * FLASH on the Local Bus
146 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
192 * port-size = 32-bits = BR2[19:20] = 11
214 * 9 columns OR2[19-21] = 010
215 * 13 rows OR2[23-25] = 100
250 * port-size = 8-bits = BR[19:20] = 01
290 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
326 * Memory space is mapped 1-1, but I/O space must start from 0.
420 /* Options are: eTSEC[0-3] */
430 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
477 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
513 "bootm $loadaddr - $fdtaddr"