Lines Matching +full:non +full:- +full:flash
1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Authors: Roy Zang <tie-fei.zang@freescale.com>
28 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
71 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
72 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
73 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
75 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
78 * Localbus non-cacheable
80 * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable
81 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
87 #define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */
97 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
98 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
103 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
118 /* NAND flash config */
173 * Memory space is mapped 1-1, but I/O space must start from 0.
218 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
253 #define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
330 "bootm $loadaddr - $fdtaddr"
339 "bootm $loadaddr - $fdtaddr"