| /openbmc/qemu/hw/ppc/ |
| H A D | ppc.c | 4 * Copyright (c) 2003-2007 Jocelyn Mayer
32 #include "qemu/main-loop.h"
33 #include "qemu/error-report.h"
44 void ppc_set_irq(PowerPCCPU *cpu, int irq, int level) in ppc_set_irq() argument
46 CPUPPCState *env = &cpu->env; in ppc_set_irq()
52 old_pending = env->pending_interrupts; in ppc_set_irq()
54 if (level) { in ppc_set_irq()
55 env->pending_interrupts |= irq; in ppc_set_irq()
57 env->pending_interrupts &= ~irq; in ppc_set_irq()
60 if (old_pending != env->pending_interrupts) { in ppc_set_irq()
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
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| H A D | img,pdc-intc.txt | 10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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| H A D | open-pic.txt | 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
19 - interrupt-controller: The presence of this property identifies the node
22 - #interrupt-cells: Specifies the number of cells needed to encode an
25 - #address-cells: Specifies the number of cells needed to encode an
27 'interrupt-map' nodes do not have to specify a parent unit address.
31 - pic-no-reset: The presence of this property indicates that the PIC
42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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| H A D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
13 bits[3:0] trigger type and level flags:
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
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| H A D | nxp,lpc3220-mic.txt | 4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
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| H A D | interrupts.txt | 5 -------------------------
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
34 -----------------------------
36 A device is marked as an interrupt controller with the "interrupt-controller"
37 property. This is a empty, boolean property. An additional "#interrupt-cells"
45 -----------
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| /openbmc/linux/drivers/irqchip/ |
| H A D | qcom-pdc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
45 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
88 __pdc_enable_intr(d->hwirq, on); in pdc_enable_intr()
110 * Level sensitive active low LOW
111 * Rising edge sensitive NOT USED
112 * Falling edge sensitive LOW
113 * Dual Edge sensitive NOT USED
114 * Level sensitive active High HIGH
115 * Falling Edge sensitive NOT USED
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| /openbmc/qemu/include/hw/intc/ |
| H A D | aspeed_vic.h | 9 * the COPYING file in the top-level directory.
33 uint64_t level; member
39 /* 0=edge, 1=level */
42 /* 0=single-edge, 1=dual-edge */
45 /* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
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| H A D | sodaville.txt | 14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
34 interrupt-controller;
35 gpio-controller;
42 * level interrupt
45 interrupt-parent = <&pcigpio>;
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| H A D | nvidia,tegra20-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-gpio
18 - nvidia,tegra30-gpio
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| H A D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
23 - const: brcm,brcmstb-gpio
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| H A D | socionext,uniphier-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
27 interrupt-controller: true
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| /openbmc/u-boot/doc/device-tree-bindings/gpio/ |
| H A D | nvidia,tegra20-gpio.txt | 4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
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| /openbmc/u-boot/include/ |
| H A D | mpc8xx_irq.h | 5 * possible level sensitive interrupts assigned and generated internally
8 * as either level or edge sensitive.
11 * through the PCI and PCI-ISA bridges.
20 /* These values must be zero-based and map 1:1 with the SIU configuration.
44 * My personal preference is CPM at level 2, which puts it above the
54 /* Some internal interrupt registers use an 8-bit mask for the interrupt
55 * level instead of a number.
57 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
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| /openbmc/qemu/hw/intc/ |
| H A D | aspeed_vic.c | 9 * the COPYING file in the top-level directory.
27 * read-modify-write sequence).
47 uint64_t new = (s->raw & s->enable); in aspeed_vic_update()
50 flags = new & s->select; in aspeed_vic_update()
52 qemu_set_irq(s->fiq, !!flags); in aspeed_vic_update()
54 flags = new & ~s->select; in aspeed_vic_update()
56 qemu_set_irq(s->irq, !!flags); in aspeed_vic_update()
59 static void aspeed_vic_set_irq(void *opaque, int irq, int level) in aspeed_vic_set_irq() argument
71 trace_aspeed_vic_set_irq(irq, level); in aspeed_vic_set_irq()
74 if (s->sense & irq_mask) { in aspeed_vic_set_irq()
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| /openbmc/linux/Documentation/virt/kvm/devices/ |
| H A D | xics.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
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| /openbmc/linux/Documentation/arch/ia64/ |
| H A D | fsys.rst | 2 Light-weight System Calls for IA-64
5 Started: 13-Jan-2003
7 Last update: 27-Sep-2003
9 David Mosberger-Tang
14 "fsys-mode". To recap, the normal states of execution are:
16 - kernel mode:
18 switched over to kernel memory. The user-level state is saved
19 in a pt-regs structure at the top of the kernel memory stack.
21 - user mode:
23 user memory. The user-level state is contained in the
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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| /openbmc/linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-v2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/irqchip/arm-gic.h>
31 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2; in vgic_v2_set_underflow()
33 cpuif->vgic_hcr |= GICH_HCR_UIE; in vgic_v2_set_underflow()
44 * - active bit is transferred as is
45 * - pending bit is
46 * - transferred as is in case of edge sensitive IRQs
47 * - set to the line-level (resample time) for level sensitive IRQs
51 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v2_fold_lr_state()
52 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; in vgic_v2_fold_lr_state()
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| /openbmc/linux/Documentation/virt/ |
| H A D | paravirt_ops.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low-level critical instructions and high-level
18 time by enabling binary patching of the low-level critical operations
23 - simple indirect call
24 These operations correspond to high-level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low-level critical instructions. They
32 - a set of macros for hand written assembly code
34 because they include sensitive instructions or some code paths in
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| /openbmc/linux/drivers/net/ethernet/freescale/enetc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
8 If compiled as module (M), the module name is fsl-enetc-core.
23 level.
25 If compiled as module (M), the module name is fsl-enetc.
38 If compiled as module (M), the module name is fsl-enetc-vf.
46 If compiled as module (M), the module name is fsl-enetc-ierb.
55 If compiled as module (M), the module name is fsl-enetc-mdio.
67 If compiled as module (M), the module name is fsl-enetc-ptp.
70 bool "ENETC hardware Time-sensitive Network support"
73 There are Time-Sensitive Network(TSN) capabilities(802.1Qbv/802.1Qci
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| /openbmc/qemu/qapi/ |
| H A D | trace.json | 1 # -*- mode: python -*-
4 # Copyright (C) 2011-2016 Lluís Vilanova <vilanova@ac.upc.edu>
7 # See the COPYING file in the top-level directory.
44 # @trace-event-get-state:
48 # @name: Event name pattern (case-sensitive glob).
54 # .. qmp-example::
56 # -> { "execute": "trace-event-get-state",
58 # <- { "return": [ { "name": "qemu_memalign", "state": "disabled", "vcpu": false } ] }
60 { 'command': 'trace-event-get-state',
65 # @trace-event-set-state:
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| /openbmc/qemu/include/hw/vfio/ |
| H A D | vfio-amd-xgbe.h | 10 * the COPYING file in the top-level directory.
17 #include "hw/vfio/vfio-platform.h"
20 #define TYPE_VFIO_AMD_XGBE "vfio-amd-xgbe"
24 * - 5 MMIO regions: MAC, PCS, SerDes Rx/Tx regs,
26 * - 2 level sensitive IRQs and optional DMA channel IRQs
|